AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 47

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

RD
RES
RFSH2/ADEN
RTS0/RTR0/PIO20
Read Strobe (output, synchronous, three-state)
RD—This pin indicates to the system that the microcontroller is
performing a memory or I/O read cycle. RD is guaranteed to not be
asserted before the address and data bus is floated during the address-
to-data transition. RD floats during a bus hold condition.
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset. When RES is
asserted, the microcontroller immediately terminates its present
activity, clears its internal logic, and CPU control is transferred to the
reset address, FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA because RES is
synchronized internally. For proper initialization, V
specifications, and CLKOUTA must be stable for more than four
CLKOUTA periods during which RES is asserted.
The microcontroller begins fetching instructions approximately 6.5
CLKOUTA periods after RES is deasserted. This input is provided with
a Schmitt trigger to facilitate power-on RES generation via an RC
network.
(Am188ES Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Asserted Low to signify a DRAM refresh bus cycle. The use
of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is
selected. Instead, the MCS3/RFSH signal is provided to the PSRAM.
ADEN—If RFSH2/ADEN is held High or left floating on power-on reset,
the AD bus (AO15–AO8 and AD7–AD0) is enabled or disabled during
the address portion of LCS and UCS bus cycles based on the DA bit in
the LMCS and UMCS registers. If the DA bit is set, the memory address
is accessed on the A19–A0 pins. This mode of operation reduces power
consumption. There is a weak internal pullup resistor on RFSH2/ADEN
so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both
addresses and data regardless of the DA bit setting. The pin is sampled
one crystal clock cycle after the rising edge of RES. RFSH2/ADEN is
three-stated during bus holds and ONCE mode.
Ready-to-Send 0 (output, asynchronous)
Ready-to-Receive 0 (output, asynchronous)
RTS0—This pin provides the Ready to Send signal for asynchronous
serial port 0 when the RTS0 bit in the AUXCON register is 1 and
hardware flow control is enabled for the port (FC bit in the serial port 0
control register is set). The RTS0 signal is asserted when the associated
serial port transmit register contains data which has not been
transmitted.
RTR0—This pin provides the Ready to Receive signal for asynchronous
serial port 0 when the RTS0 bit in the AUXCON register is 0 and
System Overview
CC
must be within
3-15