AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 108

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.3.7
Figure 7-10
7-20
Interrupt Request Register
(REQST, Offset 2Eh)
(Master Mode)
The hardware interrupt sources have interrupt request bits inside the interrupt controller.
A read from this register yields the status of these bits. The Interrupt Request register is a
read-only register. The format of the Interrupt Request register is shown in Figure 7-10.
For internal interrupts (SP0, SP1, D1/I6, D0/I5, and TMR), the corresponding bit is set to
1 when the device requests an interrupt. The bit is reset during the internally generated
interrupt acknowledge.
For INT6–INT0 external interrupts, the corresponding bit (INT4–INT0) reflects the current
value of the external signal. The device must hold this signal High until the interrupt is
serviced.
Generally the interrupt service routine signals the external device to remove the interrupt
request.
Interrupt Request Register
The REQST register is undefined on reset.
Bits 15–11: Reserved
Bit 10: Serial Port 0 Interrupt Request (SP0)—This bit indicates the interrupt state of
serial port 0. If enabled, the SP0 bit is the logical OR of all possible serial port interrupt
sources (THRE, RDR, BRK1, BRK0, FER, PER, and OER status bits).
Bit 9: Serial Port 1 Interrupt Request (SP1)—This bit indicates the interrupt state of serial
port 1. If enabled, the SP1 bit is the logical OR of all possible serial port interrupt sources
(THRE, RDR, BRK1, BRK0, FER, PER, and OER status bits).
Bits 8–4: Interrupt Requests (INT4–INT0)—When set to 1, the corresponding INT pin
has an interrupt pending (i.e., when INT0 is pending, INT0 is set).
Bit 3: DMA Channel 1/Interrupt 6 Request (D1/I6)—When set to 1, DMA channel 1 or
INT6 has an interrupt pending.
Bit 2: DMA Channel 0/Interrupt 5 Request (D0/I5)—When set to 1, DMA channel 0 or
INT5 has an interrupt pending.
Bit 1: Reserved
15
Reserved
Interrupt Control Unit
SP0
SP1
I4
7
I3
I2
I1
I0
D1/I6
Res
D0/I5
TMR
0