AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 38

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

3-6
INT0
INT1/SELECT
INT2/INTA0/PWD/PIO31
requests in priority of activity requests received by the processor. This
implies that if a HOLD request is received just as a DMA transfer begins,
the HOLD latency can be as great as 4 bus cycles. This occurs if a DMA
word transfer operation is taking place (Am186ES microcontroller only)
from an odd address to an odd address. This is a total of 16 clock cycles
or more if wait states are required. In addition, if locked transfers are
performed, the HOLD latency time is increased by the length of the
locked transfer.
For more information, see the HLDA pin description.
Maskable Interrupt Request 0 (input, asynchronous)
This pin indicates to the microcontroller that an interrupt request has
occurred. If the INT0 pin is not masked, the microcontroller transfers
program execution to the location specified by the INT0 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee interrupt recognition, the
requesting device must continue asserting INT0 until the request is
acknowledged.
Maskable Interrupt Request 1 (input, asynchronous)
Slave Select (input, asynchronous)
INT1—This pin indicates to the microcontroller that an interrupt request
has occurred. If INT1 is not masked, the microcontroller transfers
program execution to the location specified by the INT1 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee interrupt recognition, the
requesting device must continue asserting INT1 until the request is
acknowledged.
SELECT—When the microcontroller interrupt control unit is operating
as a slave to an external interrupt controller, this pin indicates to the
microcontroller that an interrupt type appears on the address and data
bus. The INT0 pin must indicate to the microcontroller that an interrupt
has occurred before the SELECT pin indicates to the microcontroller
that the interrupt type appears on the bus.
Maskable Interrupt Request 2 (input, asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
Pulse Width Demodulator (input, Schmitt trigger)
INT2—This pin indicates to the microcontroller that an interrupt request
has occurred. If the INT2 pin is not masked, the microcontroller transfers
program execution to the location specified by the INT2 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee interrupt recognition, the
requesting device must continue asserting INT2 until the request is
acknowledged. INT2 becomes INTA0 when INT0 is configured in
cascade mode.
System Overview