AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 57

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

3.4
3.4.1
3.4.2
High during a refresh cycle. The A19–A0 bus is not used during refresh cycles. The LMCS
register must be configured to external Ready ignored (R2=1) with one wait state (R1–
R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1. See section 5.5.2 on
page 5-6.
CLOCK AND POWER MANAGEMENT UNIT
The clock and power management unit of the Am186ES and Am188ES microcontrollers
includes a phase-locked loop (PLL) and a second programmable system clock output
(CLKOUTB).
Phase-Locked Loop (PLL)
In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal
clock. Because of the internal PLL on the Am186ES and Am188ES microcontrollers, the
internal clock generated by the microcontroller (CLKOUTA) is the same frequency as the
crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45/55% (worst case)
duty cycle intermediate system clock of the same frequency. This feature removes the need
for an external 2x oscillator, thereby reducing system cost. The PLL is reset during power-
on reset by an on-chip power-on reset (POR) circuit.
Crystal-Driven Clock Source
The internal oscillator circuit of the microcontroller is designed to function with a parallel
resonant fundamental or third overtone crystal. Because of the PLL, the crystal frequency
is equal to the processor frequency. Replacement of a crystal with an LC or RC equivalent
is not recommended.
The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) which
provides, along with the external feedback loading, the necessary phase shift (Figure 3-5).
In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180
degrees out of phase of the input signal (X1). The external feedback network provides an
additional 180 degree phase shift. In an ideal system, the input to X1 will have 360 or zero
degrees of phase shift.
The external feedback network is designed to be as close as possible to ideal. If the
feedback network is not providing necessary phase shift, negative feedback will dampen
the output of the amplifier and negatively affect the operation of the clock generator. Values
for the loading on X1 and X2 must be chosen to provide the necessary phase shift and
crystal operation.
System Overview
3-25