AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 133

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

9.1
9.2
Table 9-1
CHAPTER
9
DMA CONTROLLER
OVERVIEW
Direct memory access (DMA) permits transfer of data between memory and peripherals
without CPU involvement. The DMA unit in the Am186ES and Am188ES microcontrollers
provides two high-speed DMA channels. Data transfers can occur between memory and
I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/
O-to-I/O). Either bytes or words can be transferred to or from even or odd addresses on
the Am186ES microcontroller. (The Am188ES microcontroller does not support word
transfers.) Two bus cycles (a minimum of eight clocks) are necessary for each data transfer.
Each channel accepts a DMA request from one of three sources: the channel request pin
(DRQ1–DRQ0), timer 2, or an asynchronous serial port. The two DMA channels can be
programmed with different priorities to resolve simultaneous DMA requests, and transfers
on one channel can interrupt the other channel.
DMA OPERATION
The format of the DMA control block is shown in Table 9-1. Six registers in the peripheral
control block define the operation of each channel. The DMA registers consist of a 20-bit
source address (2 registers), a 20-bit destination address (2 registers), a 16-bit transfer
count register, and a 16-bit control register.
DMA Controller Register Summary
The DMA transfer count register (DTC) specifies the number of DMA transfers to be
performed. On the Am186ES, up to 64 Kbytes or 64 Kwords can be transferred with
automatic termination. The Am188ES does not support word transfers.
The DMA control registers define the channel operations (see Figure 9-1). All registers
can be modified or altered during any DMA activity. Any changes made to these registers
are reflected immediately in DMA operation.
Offset from PCB
CAh
DAh
C8h
D8h
C6h
D6h
C4h
D4h
C2h
D2h
C0h
D0h
Register
Mnemonic
D0CON
D1CON
D0TC
D1TC
D0DSTH
D1DSTH
D0DSTL
D1DSTL
D0SRCH
D1SRCH
D0SRCL
D1SRCL
DMA Controller
Register Name
DMA 0 Control
DMA 1 Control
DMA 0 Transfer Count
DMA 1 Transfer Count
DMA 0 Destination Address High
DMA 1 Destination Address High
DMA 0 Destination Address Low
DMA 1 Destination Address Low
DMA 0 Source Address High
DMA 1 Source Address High
DMA 0 Source Address Low
DMA 1 Source Address Low
9-1