AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 43

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

PCS3/RTS1/RTR1/PIO19
PCS5/A1/PIO3
PCS6/A2/PIO2
Peripheral Chip Select 3 (output, synchronous)
Ready-to-Send 1 (output, asynchronous)
Ready-to-Receive 1 (output, asynchronous)
PCS3—This pin provides the Peripheral Chip Select 3 signal to the
system when hardware flow control is not enabled for asynchronous
serial port 1. The PCS3 signal indicates to the system that a memory
access is in progress to the corresponding region of the peripheral
memory block (either I/O or memory address space). The base address
of the peripheral memory block is programmable. PCS3 is held High
during a bus hold or reset condition.
Unlike the UCS and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus. Note also that each peripheral chip select
asserts over a 256-byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and 80C188
microcontrollers.
RTS1—This pin provides the Ready to Send signal for asynchronous
serial port 1 when the RTS1 bit in the AUXCON register is 1 and
hardware flow control is enabled for the port (FC bit in the serial port 1
control register is set). The RTS1 signal is asserted when the associated
serial port transmit register contains data which has not been
transmitted.
RTR1—This pin provides the Ready to Receive signal for asynchronous
serial port 1 when the RTS1 bit in the AUXCON register is 0 and
hardware flow control is enabled for the port (FC bit in the serial port 1
control register is set). The RTR1 signal is asserted when the associated
serial port receive register does not contain valid, unread data.
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory access is in
progress to the sixth region of the peripheral memory block (either I/O
or memory address space). The base address of the peripheral memory
block is programmable. PCS5 is held High during a bus hold condition.
It is also held High during reset.
Unlike the UCS and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus. Note also that each peripheral chip select
asserts over a 256-byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and 80C188
microcontrollers.
A1—When the EX bit in the MCS and PCS auxiliary register is 0, this
pin supplies an internally latched address bit 1 to the system. During a
bus hold condition, A1 retains its previously latched value.
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory access is in
progress to the seventh region of the peripheral memory block (either
I/O or memory address space). The base address of the peripheral
memory block is programmable. PCS6 is held High during a bus hold
condition or reset.
System Overview
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