AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 41

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

MCS3/RFSH/PIO25
NMI
If they are not programmed as PIOs and if MCS0 is programmed for
the whole middle chip-select range, these signals operate normally.
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
MCS3—This pin indicates to the system that a memory access is in
progress to the fourth region of the midrange memory block. The base
address and size of the midrange memory block are programmable.
On the Am186ES microcontroller, MCS3 is configured for 8-bit or 16-
bit bus size by the auxiliary configuration register. MCS3 is held High
during a bus hold condition. In addition, this pin has a weak internal
pullup resistor that is active during reset.
This signal functions like the corresponding signal in the Am186EM and
Am188EM microcontrollers except that if MCS0 is programmed for the
entire middle chip-select range, then this signal is available as a PIO.
If MCS3 is not programmed as a PIO and if MCS0 is programmed for
the entire middle chip-select range, this signal operates normally.
Depending on chip configuration, this signal can serve as a memory
RFSH.
RFSH—This pin provides a signal timed for auto refresh to PSRAM or
DRAM devices. It is only enabled to function as a refresh pulse when
the PSRAM or DRAM mode bit is set. An active Low pulse is generated
for 1.5 clock cycles with an adequate deassertion period to ensure that
overall auto refresh cycle time is met.
This signal functions like the RFSH signal in the Am186EM and
Am188EM microcontrollers except that the DRAM row address is not
driven on DRAM refreshes. This pin is not three-stated during a bus
hold condition.
Nonmaskable Interrupt (input, synchronous, edge-sensitive)
This pin indicates to the microcontroller that an interrupt request has
occurred. The NMI signal is the highest priority hardware interrupt and,
unlike the INT6–INT0 pins, cannot be masked. The microcontroller
always transfers program execution to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt vector
table when NMI is asserted.
Although NMI is the highest priority interrupt source, it does not
participate in the priority resolution process of the maskable interrupts.
There is no bit associated with NMI in the interrupt in-service or interrupt
request registers. This means that a new NMI request can interrupt an
executing NMI interrupt service routine. As with all hardware interrupts,
the IF (interrupt flag) is cleared when the processor takes the interrupt,
disabling the maskable interrupt sources. However, if maskable
interrupts are reenabled by software in the NMI interrupt service routine,
via the STI instruction for example, the fact that an NMI is currently in
service will not have any effect on the priority resolution of maskable
interrupt requests. For this reason, it is strongly advised that the interrupt
service routine for NMI does not enable the maskable interrupts.
System Overview
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