AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 153

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

Table 10-4
Bit 8: Transmitter Ready Interrupt Enable (TXIE)—When this bit is set, the serial port
generates an interrupt request whenever the transmit holding register is empty (THRE bit
in the status register is set), indicating that the transmitter is available to accept a new
character for transmission. When this bit is reset, the serial port does not generate transmit
interrupt requests . Interrupt requests continue to be generated as long as the TXIE bit is
set and the transmitter does not contain valid data to transmit, i.e., the THRE bit in the
status register remains set.
Bit 7: Receive Data Ready Interrupt Enable (RXIE) —When this bit is set, the serial port
generates an interrupt request whenever the receive register contains valid data (RDR bit
in the status register is set). When this bit is reset, the serial port does not generate receive
interrupt requests . Interrupt requests continue to be generated as long the RXIE bit is set
and the receiver contains unread data (the RDR bit in the status register is set).
Bit 6: Transmit Mode (TMODE)—When this bit is set, the transmit section of the serial
port is enabled. When this bit is reset, the transmitter and transmit interrupt requests are
disabled .
Bit 5: Receive Mode (RMODE)—When this bit is set, the receive section of the serial port
is enabled. When this bit is reset, the receiver is disabled .
Bit 4: Even Parity (EVN)—This bit determines the parity sense. When EVN is set, even
parity checking is enforced (even number of 1s in frame). When EVN is reset, odd parity
checking is enforced (odd number of 1s in frame).
Note: This bit is valid only when the PE bit is set (parity enabled).
Bit 3: Parity Enable (PE)—When this bit is set, parity checking is enabled. When this bit
is reset, parity checking is disabled.
Bits 2–0: Mode of Operation (MODE)—This field determines the operating mode for the
serial port. The valid modes and their descriptions are shown in Table 10-4.
Mode 1 supports 7 data bits when parity is enabled or 8 data bits with parity disabled. When
using parity, the eighth bit becomes the parity bit and is generated for transmits, or checked
for receives automatically by the processor.
Serial Port MODE Settings
Mode 2—When configured in this mode, the serial port receiver will not complete a data
reception unless the ninth data bit is set (High). Any character received with the ninth data
MODE Description
0
1
2
3
4
5
6
7
Reserved
Data Mode 1
Data Mode 2
Data Mode 3
Data Mode 4
Reserved
Reserved
Reserved
Asynchronous Serial Port
Data
Bits
7 or 8 1 or 0
8 or 9 1 or 0
9
7
Parity
Bits
N/A
N/A
Stop
Bits
1
1
1
1
10-7