AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 96

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AM186ES

Manufacturer Part Number
AM186ES
Description
microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
Manufacturer
Advanced Micro Devices
Datasheets

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7.1.4.8
7.1.5
Figure 7-1
7-8
Internal lock
AD7–AD0
S0–S2
INTA
ESC Opcode Exception (Interrupt Type 07h)
Generated if execution of ESC opcodes (D8h–DFh) is attempted. The microcontrollers do
not check the escape opcode trap bit. The return address of this exception points to the
ESC instruction that caused the exception. If a segment override prefix preceded the ESC
instruction, the return address points to the segment override prefix.
Note: All numeric coprocessor opcodes cause a trap. The Am186ES and Am188ES
microcontrollers do not support the numeric coprocessor interface.
Interrupt Acknowledge
Interrupts can be acknowledged in two different ways—the internal interrupt controller can
provide the interrupt type or an external interrupt controller can provide the interrupt type.
The processor requires the interrupt type as an index into the interrupt vector table.
When the internal interrupt controller is supplying the interrupt type, no interrupt
acknowledge bus cycles are generated. The only external indication that an interrupt is
being serviced is the processor reading the interrupt vector table.
When an external interrupt controller is supplying the interrupt type, the processor
generates two interrupt acknowledge bus cycles (see Figure 7-1). The interrupt type is
written to the AD7–AD0 lines by the external interrupt controller during the second bus cycle.
Interrupt acknowledge bus cycles have the following characteristics:
External Interrupt Acknowledge Bus Cycles
Notes:
1. ALE is active for each INTA cycle.
2. RD is inactive.
The two interrupt acknowledge cycles are locked.
Two idle states are always inserted between the two interrupt acknowledge cycles.
Wait states are inserted if READY is not returned to the processor.
Acknowledge
T1
Interrupt
T2
Interrupt Control Unit
T3
T4
Ti
Ti
Acknowledge
T1
Interrupt
T2
Interrupt
Type
T3
T4

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