AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 56

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

Table 3-3
3.3.3
3.3.4
3-24
Programming Am186ES Microcontroller Bus Width
Byte Write Enables
The Am186ES microcontroller provides two signals that act as byte write enables—WHB
(Write High Byte, AD15–AD8) and WLB (Write Low Byte, AD7–AD0). WHB is the logical
OR of BHE and WR (WHB is Low when both BHE and WR are Low). WLB is the logical
OR of A0 and WR (WLB is Low when both A0 and WR are both Low).
The Am188ES microcontroller provides one signal for byte write enables—WB (Write Byte).
WB is the logical AND of WHB and WLB, which are not present on the Am188ES
microcontroller.
The byte write enables are driven in conjunction with the nonmultiplexed address bus as
required for the write timing requirements of common SRAMs.
Pseudo Static RAM (PSRAM) Support
The Am186ES and Am188ES microcontrollers support the use of PSRAM devices in low
memory chip-select (LCS) space only. When PSRAM mode is enabled, the timing for the
LCS signal is modified by the chip select control unit to provide a CS precharge period
during PSRAM accesses. The 40-MHz timing of the Am186ES and Am188ES
microcontrollers is appropriate to allow 70-ns PSRAM to run with one wait state. PSRAM
mode is enabled through a bit in the Low Memory Chip Select (LMCS) register. (See section
5.5.2 on page 5-6.) The PSRAM feature is disabled on CPU reset.
In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also
require periodic refresh of all internal row addresses to retain their data. Although refresh
of PSRAM can be accomplished several ways, the Am186ES and Am188ES
microcontrollers implement auto refresh only. The microcontrollers generate a refresh
signal, RFSH, to the PSRAM devices when PSRAM mode and the refresh control unit are
enabled. No refresh address is required by the PSRAM when using the auto refresh
mechanism. The RFSH signal is multiplexed with the MCS3 signal pin. When PSRAM mode
is enabled, MCS3 is not available for use as a chip select signal.
The refresh control unit must be programmed before accessing PSRAM in LCS space. The
refresh counter in the Clock Pre-Scaler (CDRAM) register must be configured with the
required refresh interval value. The ending address of LCS space and the ready and wait-
state generation in the LMCS register must also be programmed.
The refresh counter reload value in the CDRAM register should not be set to less than 18
(12h) in order to provide time for processor cycles within refresh. The refresh address
counter must be set to 0000h to prevent another chip select from asserting. LCS is held
Space
Other
UCS
LCS
I/O
AUXCON
IOSIZ
Field
MSIZ
LSIZ
–
System Overview
Value
–
0
1
0
1
0
1
Width
16 bits not configurable
16 bits default
16 bits default
16 bits default
Bus
8 bits
8 bits
8 bits
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