AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 89

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.1
7.1.1
7.1.1.1
CHAPTER
7
INTERRUPT CONTROL UNIT
OVERVIEW
The Am186ES and Am188ES microcontrollers can receive interrupt requests from a variety
of sources, both internal and external. The internal interrupt controller arranges these
requests by priority and presents them one at a time to the CPU.
There are up to eight external interrupt sources on the Am186ES and Am188ES
microcontrollers—seven maskable interrupt pins (INT6–INT0) and one nonmaskable
interrupt (NMI) pin. There are eight internal interrupt sources that are not connected to
external pins—three timers, two DMA channels, two asynchronous serial ports, and the
watchdog timer NMI. INT5 and INT6 are multiplexed with DRQ0 and DRQ1 respectively.
These two interrupts are available if the associated DMA is not enabled or is being used
with internal synchronization.
The Am186ES and Am188ES microcontrollers provide up to six interrupt sources that are
not present on the 80C186 and 80C188 microcontrollers:
The seven maskable interrupt request pins can be used as direct interrupt requests. INT4–
INT0 can be either edge triggered or level triggered. INT6 and INT5 are edge triggered
only. In addition, INT0 and INT1 can be configured in cascade mode for use with an external
82C59A-compatible interrupt controller. When INT0 is configured in cascade mode, the
INT2 pin is automatically configured in its INTA0 function. When INT1 is configured in
cascade mode, the INT3 pin is automatically configured in its INTA1 function. An external
interrupt controller can be used as the system master by programming the internal interrupt
controller to operate in slave mode. INT6–INT4 are not available in slave mode.
Interrupts are automatically disabled when an interrupt is taken. Interrupt-service routines
(ISRs) may re-enable interrupts by setting the IF flag. This allows interrupts of greater or
equal priority to interrupt the currently executing ISR. Interrupts from the same source are
disabled as long as the corresponding bit in the interrupt in-service register is set. INT1
and INT0 provide a special bit to enable special fully nested mode. When configured in
special fully nested mode, the interrupt source may generate a new interrupt regardless of
the setting of the in-service bit.
Definitions of Interrupt Terms
The following definitions cover some of the terminology that is used in describing the
functionality of the interrupt controller. Table 7-1 contains information regarding the
reserved interrupts.
Interrupt Type
An 8-bit interrupt type identifies each of the 256 possible interrupts.
INT4, INT5, INT6; additional external interrupt pins that operate like the INT3–INT0 pins
An internal, watchdog timer interrupt
An internal interrupt from each of the two serial ports
Interrupt Control Unit
7-1