AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 102

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.3.1
Figure 7-4
7-14
INT0 and INT1 Control Registers
(I0CON, Offset 38h, I1CON, Offset 3Ah)
(Master Mode)
The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to
interrupt type 0Dh.
When cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin
becomes INTA0, the interrupt acknowledge for INT0.
When cascade mode is enabled for INT1 by setting the C bit of I1CON to 1, the INT3 pin
becomes INTA1, the interrupt acknowledge for INT1.
INT0 and INT1 Control Registers
The value of I0CON and I1CON at reset is 000Fh.
Bits 15–7: Reserved—Set to 0.
Bit 6: Special Fully Nested Mode (SFNM)—When set to 1, enables special fully nested
mode for INT0 or INT1.
Bit 5: Cascade Mode (C)—When set to 1, this bit enables cascade mode for INT0 or INT1.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT0 or INT1 interrupt request as edge- or level-sensitive. A 1 in this bit
configures INT0 or INT1 as an active High, level-sensitive interrupt. A 0 in this bit configures
INT0 or INT1 as a Low-to-High, edge-triggered interrupt. In either case, INT0 or INT1 must
remain High until they are acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT0 or INT1 signal can cause an
interrupt. A 1 in this bit masks this interrupt source, preventing INT0 or INT1 from causing
an interrupt. A 0 in this bit enables INT0 or INT1 interrupts.
This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in Section
7.3.10 on page 7-24.
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of INT0 or INT1
relative to the other interrupt signals, as shown in Table 7-3 on page 7-18.
15
Reserved
Interrupt Control Unit
7
SFNM
C
LTM
MSK
PR2
PR1
PR0
0