AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 155

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

10.2.2
Figure 10-4
Serial Port 0/1 Status Registers
(SP0STS/SP1STS, Offset 82h/12h)
The Serial Port Status Registers provide information about the current status of the
associated serial port. The THRE and TEMT fields provide the software with information
about the state of the transmitter. The BRK1, BRK0, RB8, RDR, FER, OER, and PER bits
provide information about the receiver. The HS0 bit reflects the value of the serial port’s
associated CTS/ENRX signal. The THRE, TEMT, and HS0 bits are updated during each
processor cycle. The format of the Serial Port Status Register is shown in Figure 10-4.
Serial Port 0/1 Status Register
Bits 15–11: Reserved
Bit 10: Long Break Detected (BRK1)—This bit is set when a long break is detected on
the asynchronous serial interface. A long break is defined as a Low signal on the RXD pin
for greater than 2M+3 bit times, where M = (start bit + # data bits + # parity bits + stop bit).
If the serial port is receiving a character when the break begins, the reception of the
character will be completed (generating a framing error) before timing for the break begins.
To guarantee detection with the specified 2M+3 bit times, the break must begin outside of
a frame.
Note: This bit should be reset by software.
Bit 9: Short Break Detected (BRK0)—This bit is set when a short break is detected on
the asynchronous serial interface. A short break is defined as a Low signal on the RXD pin
for greater than M bit times, where M = (start bit + # data bits + # parity bits + stop bit).
If the serial port is receiving a character when the break begins, the reception of the
character will be completed (generating a framing error) before timing for the break begins.
To guarantee detection with the specified M bit times, the break must begin outside of a
frame.
Note: This bit should be reset by software.
Bit 8: Received Bit 8 (RB8)—This bit contains the ninth data bit received in modes 2 and
3. (See Serial Port Control register definition.)
Note: This bit should be reset by software.
Bit 7: Receive Data Ready (RDR)—When this bit is set, the corresponding Receive Data
register contains valid data. This field is read-only. The RDR bit can only be reset by reading
the associated SP0RD/SP1RD register.
Bit 6: Transmit Holding Register Empty (THRE)—When this bit is set, the transmit
holding register is ready to accept data for transmission. This field is read-only .
15
Reserved
BRK1
BRK0
RB8
Asynchronous Serial Port
RDR
7
THRE
FER
OER
PER
TEMT
HS0
Res.
0
10-9