AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 50

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

3-18
UCS/ONCE1
UZI/PIO26
V
WHB
WLB/WB
CC
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This pin indicates to the system that a memory access is in
progress to the upper memory block. The base address and size of the
upper memory block are programmable up to 512 Kbytes. UCS is held
High during a bus hold condition.
After reset, UCS is active for the 64 Kbyte memory range from F0000h
to FFFFFh, including the reset address of FFFF0h.
ONCE1—During reset this pin and LCS/ONCE0 indicate to the
microcontroller the mode in which it should operate. ONCE0 and
ONCE1 are sampled on the rising edge of RES. If both pins are asserted
Low, the microcontroller enters ONCE mode. Otherwise, it operates
normally. In ONCE mode, all pins assume a high-impedance state and
remain in that state until a subsequent reset occurs. To guarantee that
the microcontroller does not inadvertently enter ONCE mode, ONCE1
has a weak internal pullup resistor that is active only during a reset.
This pin is not three-stated during a bus hold condition.
Upper Zero Indicate (output, synchronous)
This pin lets the designer determine if an access to the interrupt vector
table is in progress by ORing it with bits 15–10 of the address and data
bus (AD15–AD10 on the 186 and AO15–AO10 on the 188). UZI is the
logical AND of the inverted A19–A16 bits. It asserts in the first period
of a bus cycle and is held throughout the cycle.
Power Supply (input)
These pins supply power (+5 V) to the microcontroller.
Write High Byte, Am186ES Microcontroller Only
(output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of the data bus
(upper, lower, or both) participate in a write cycle. In 80C186
microcontroller designs, this information is provided by BHE, AD0, and
WR. However, by using WHB and WLB, the standard system interface
logic and external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical OR of BHE and
WR. This pin floats during reset.
Write Low Byte, Am186ES Microcontroller
(output, three-state, synchronous)
Write Byte, Am188ES Microcontroller
(output, three-state, synchronous)
WLB—This pin and WHB indicate to the system which bytes of the data
bus (upper, lower, or both) participate in a write cycle. In 80C186
microcontroller designs, this information is provided by BHE, AD0, and
WR. However, by using WHB and WLB, the standard system interface
logic and external address latch that were required are eliminated.
WLB is asserted with AD7–AD0. WLB is the logical OR of AD0 and WR.
This pin floats during reset.
System Overview