AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 36

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

3-4
CLKOUTB
CTS0/ENRX0/PIO21
DEN/DS/PIO5
DRQ0/INT5/PIO12 DMA Request 0 (input, synchronous, level-sensitive)
All AC timing specs that use a clock relate to CLKOUTA.
Clock Output B (output, synchronous)
This pin supplies an additional clock with a delayed output compared
to CLKOUTA. Depending upon the value of the system configuration
register (SYSCON), CLKOUTB operates at either the crystal input
frequency (X1), the power-save frequency, or is three-stated. CLKOUTB
remains active during reset and bus hold conditions.
CLKOUTB is not used for AC timing specs.
Clear-to-Send 0 (input, asynchronous)
Enable-Receiver-Request 0 (input, asynchronous)
CTS0—This pin provides the Clear to Send signal for asynchronous
serial port 0 when the ENRX0 bit in the AUXCON register is 0 and
hardware flow control is enabled for the port (FC bit in the serial port 0
control register is set). The CTS0 signal gates the transmission of data
from the associated serial port transmit register. When CTS0 is
asserted, the transmitter will begin transmission of a frame of data, if
any is available. If CTS0 is deasserted, the transmitter holds the data
in the serial port transmit register. The value of CTS0 is checked only
at the beginning of the transmission of the frame.
ENRX0—This pin provides the Enable Receiver Request for
asynchronous serial port 0 when the ENRX0 bit in the AUXCON register
is 1 and hardware flow control is enabled for the port (FC bit in the serial
port 0 control register is set). The ENRX0 signal enables the receiver
for the associated serial port.
Data Enable (output, three-state, synchronous)
Data Strobe (output, three-state, synchronous)
DEN—This pin supplies an output enable to an external data-bus
transceiver. DEN is asserted during memory, I/O, and interrupt
acknowledge cycles. DEN is deasserted when DT/R changes state.
DEN floats during a bus hold or reset condition.
DS—The data strobe provides a signal where the write cycle timing is
identical to the read cycle timing. When used with other control signals,
DS provides an interface for 68K-type peripherals without the need for
additional system interface logic.
When DS is asserted, addresses are valid. When DS is asserted on
writes, data is valid. When DS is asserted on reads, data can be
asserted on the AD bus.
Note: This pin resets to DEN.
Maskable Interrupt Request 5 (input, asynchronous, edge-triggered)
DRQ0—This pin indicates to the microcontroller that an external device
is ready for DMA channel 0 to perform a transfer. DRQ0 is level-
triggered and internally synchronized. DRQ0 is not latched and must
remain active until serviced.
INT5—If DMA 0 is not enabled or DMA 0 is not being used with external
synchronization, INT5 can be used as an additional external interrupt
System Overview