AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 94

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.1.3
7.1.3.1
7.1.3.2
7-6
Interrupt Priority
Table 7-1 shows the predefined types and overall priority structure for the Am186ES and
Am188ES microcontrollers. Nonmaskable interrupts (interrupt types 0–7) are always higher
priority than maskable interrupts. Maskable interrupts have a programmable priority that
can override the default priorities relative to one another.
The levels of interrupt priority are as follows:
Nonmaskable Interrupts and Software Interrupt Priority
The nonmaskable interrupts from 00h to 07h and software interrupts (INT instruction)
always take priority over the maskable hardware interrupts. Within the nonmaskable and
software interrupts, the trace interrupt has the highest priority, followed by the NMI interrupt,
followed by the remaining nonmaskable and software interrupts.
After the trace interrupt and the NMI interrupt, the remaining software exceptions are
mutually exclusive and can only occur one at a time, so there is no further priority
breakdown.
Maskable Hardware Interrupt Priority
Beginning with interrupt type 8 (the timer 0 interrupt), the maskable hardware interrupts
have both an overall priority (see Table 7-1) and a programmable priority. The
programmable priority is the primary priority for maskable hardware interrupts. The overall
priority is the secondary priority for maskable hardware interrupts.
Since all maskable interrupts are set to a programmable priority of seven on reset, the
overall priority of the interrupts determines the priority in which each interrupt is granted by
the interrupt controller until programmable priorities are changed by reconfiguring the
control registers.
The overall priority levels shown in Table 7-1 are not the same as the programmable priority
level that is associated with each maskable hardware interrupt. Each of the maskable
hardware interrupts has a programmable priority from zero to seven, with zero being the
highest priority (see Table 7-3 on page 7-18).
For example, if the INT6–INT0 interrupts are all changed to programmable priority six and
no other programmable priorities are changed from the reset value of seven, then the INT6–
INT0 interrupts take precedence over all other maskable interrupts. (Within INT6–INT0, the
hierarchy is as follows: INT5>INT6>INT0>INT1>INT2>INT3>INT4.)
Interrupt priority for nonmaskable interrupts and software interrupts
Interrupt priority for maskable hardware interrupts
Interrupt Control Unit