ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 89

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
DMACounter
14.4.3 HcTransferCounter register (R/W: 22h/A2h)
Enable
R/W
7
0
Table 67.
Table 68.
Regardless of PIO or DMA data transfer modes, this register is used to initialize the
number of bytes to be transferred to or from the ISTL, INTL or ATL buffer RAM. For the
count value loaded in the register to take effect, the HCD is required to set bit 7 of the
HcDMAConfiguration register to logic 1. When the count value has reached, the host
controller must generate an internal EOT signal to set bit 2 of the HcμPInterrupt register,
AllEOTInterrupt, and update the HcBufferStatus register. The bit allocation of the
HcTransferCounter register is given in
Code (Hex): 22 — read
Code (Hex): A2 — write
Bit
15 to 8
7
6 to 5
4
3 to 1
0
Bit 3
0
0
0
0
1
R/W
6
0
BurstLen[1:0]
Symbol
-
DMACounterEnable
BurstLen[1:0]
DMAEnable
Buffer_Type_Select[2:0] See
DMAReadWriteSelect
HcDMAConfiguration register: bit description
Buffer_Type_Select[2:0]: bit description
Bit 2
0
0
1
1
X
R/W
5
0
Rev. 07 — 29 September 2009
Bit 1
0
1
0
1
X
Enable
DMA
R/W
Description
reserved
0 — reserved
1 — DMA counter is enabled. Once the counter is enabled, the
HCD must initialize the HcTransferCounter register to a
non-zero value for DREQ to be raised after the DMAEnable bit
is set to HIGH.
00 — single-cycle burst DMA
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
I/O bus with 32-bit data path width supports only single and
four cycle DMA burst.
0 — DMA is disabled
1 — DMA is enabled
This bit must be reset when the DMA transfer is completed.
0 — read from the buffer memory of the host controller
1 — write to the buffer memory of the host controller
4
0
Buffer Type
ISTL0 (default)
ISTL1
INTL
ATL
direct addressing
Table
Table
68.
R/W
69.
3
0
Buffer_Type_Select[2:0]
Single-chip USB OTG controller
R/W
2
0
© ST-ERICSSON 2009. All rights reserved.
R/W
1
0
ISP1362
WriteSelect
DMARead
R/W
89 of 147
0
0