ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 82

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 60.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhStatus register: bit allocation
14.3.3 HcRhStatus register (R/W: 14h/94h)
CRWE
DRWE
R/W
31
23
15
W
0
0
7
-
-
-
-
Table 59.
The HcRhStatus register is divided into two parts. The lower word of a double-word
represents the hub status field, and the upper word represents the hub status change
field. Reserved bits should always be written as logic 0. See
the register.
Code (Hex): 14 — read
Code (Hex): 94 — write
Bit
31 to 19
18 to 16
15 to 3
2 to 0
30
22
14
6
-
-
-
-
-
-
-
-
Symbol
-
PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is affected by a
-
DR[2:0]
HcRhDescriptorB register: bit description
29
21
13
5
-
-
-
-
-
-
-
-
Rev. 07 — 29 September 2009
Description
reserved
global power control command when PowerSwitchingMode is set. When
set, the power state of the port is only affected by per-port power control
(Set/ClearPortPower). When cleared, the port is controlled by the global
power switch (Set/ClearGlobalPower). If the device is configured to global
switching mode (PowerSwitchingMode = 0), this field is not valid.
Bit 2 — ganged-power mask on port 2
Bit 1 — ganged-power mask on port 1
Bit 0 — reserved
reserved
DeviceRemovable: Each bit is dedicated to a port of the root hub. When
cleared, the attached device is removable. When set, the attached device
is not removable.
Bit 2 — device attached to port 2
Bit 1 — device attached to port 1
Bit 0 — reserved
reserved
reserved
28
20
12
4
-
-
-
-
-
-
-
-
reserved
reserved
27
19
11
3
-
-
-
-
-
-
-
-
Single-chip USB OTG controller
26
18
10
2
-
-
-
-
-
-
-
-
Table 60
© ST-ERICSSON 2009. All rights reserved.
CCIC
R/W
OCI
25
17
for bit allocation of
R
0
9
1
0
-
-
-
-
ISP1362
LPSC
R/W
R/W
LPS
82 of 147
24
16
0
8
0
0
-
-
-
-