ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 111

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 120. DcDMAConfiguration register: bit allocation
[1]
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
15.1.6 DcDMAConfiguration (R/W: F1h/F0h)
CNTREN
R/W
R/W
0
0
15
7
[1]
[1]
Table 119. DcInterruptEnable register: bit description
This command defines the DMA configuration of the peripheral controller, and enables or
disables DMA transfers. The command accesses the DcDMAConfiguration register, which
consists of two bytes. The bit allocation is given in
bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write or read DMA Configuration
Transaction — write or read 2 bytes (code or data)
Bit
31 to 24
23 to 10
9
8
7
6
5
4
3
2
1
0
SHORTP
R/W
R/W
0
0
14
6
[1]
[1]
EPDIX[3:0]
Symbol
-
IEP14 to IEP1
IEP0IN
IEP0OUT
-
SP_IEEOT
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
R/W
0
13
5
-
-
[1]
Rev. 07 — 29 September 2009
Logic 1 enables interrupts from the indicated endpoint. Logic 0
Logic 1 enables interrupt on detecting a short packet. Logic 0
Logic 1 enables interrupt on detecting a resume state. Logic 0
Description
reserved; must write logic 0
disables interrupts from the indicated endpoint.
Logic 1 enables interrupts from the control IN endpoint. Logic 0
disables interrupts from the control IN endpoint.
Logic 1 enables interrupts from the control OUT endpoint. Logic 0
disables interrupts from the control OUT endpoint.
reserved
disables interrupt.
Logic 1 enables 1 ms interrupts on detecting pseudo SOF. Logic 0
disables interrupts.
Logic 1 enables interrupt on the SOF detection. Logic 0 disables
interrupt.
Logic 1 enables interrupt on the EOT detection. Logic 0 disables
interrupt.
Logic 1 enables interrupt on detecting a suspend state. Logic 0
disables interrupt.
disables interrupt.
Logic 1 enables interrupt on detecting a bus reset. Logic 0 disables
interrupt.
R/W
0
12
4
-
-
[1]
DMAEN
R/W
11
3
0
-
-
reserved
Table
reserved
Single-chip USB OTG controller
120. A bus reset will clear
10
2
-
-
-
-
© ST-ERICSSON 2009. All rights reserved.
R/W
0
9
1
-
-
[1]
BURSTL[1:0]
ISP1362
111 of 147
R/W
0
8
0
-
-
[1]