ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 53

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
12.3.4 Endpoint initialization
12.3.5 Endpoint I/O mode access
12.3.6 Special actions on control endpoints
Table 17.
In response to standard USB request Set Interface, the firmware must program all the 16
ECRs of the peripheral controller in sequence (see
enabled or not. The hardware then automatically allocates the buffer memory storage
space.
If all endpoints have successfully been configured, the firmware must return an empty
packet to the control IN endpoint to acknowledge success to the host. If there are errors in
the endpoint configuration, the firmware must stall the control IN endpoint.
When reset by the hardware or by the USB bus occurs, the peripheral controller disables
all endpoints and clears all ECRs, except the control endpoint that is fixed and always
enabled.
An endpoint initialization can be done at any time. It is, however, valid only after
enumeration.
When an endpoint event occurs (a packet is transmitted or received), the associated
endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The
firmware then responds to the interrupt and selects the endpoint for processing.
The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR). The
ESR also contains information on the status of the endpoint buffer.
For an OUT (= receive) endpoint, the packet length and packet data can be read from the
peripheral controller by using the Read Buffer command. When the whole packet has
been read, the firmware sends a Clear Buffer command to enable the reception of new
packets.
For an IN (= transmit) endpoint, the packet length and data to be sent can be written to the
peripheral controller by using the Write Buffer command. When the whole packet has
been written to the buffer, the firmware sends a Validate Buffer command to enable data
transmission to the host.
Control endpoints require special firmware actions. The arrival of a set-up packet flushes
the IN buffer, and disables the Validate Buffer and Clear Buffer commands for the control
IN and OUT endpoints. The microprocessor must re-enable these commands by sending
an acknowledge set-up command to both the control endpoints.
This ensures that the last set-up packet stays in the buffer and that no packets can be
sent back to the host, until the microprocessor has explicitly acknowledged that it has
received the set-up packet.
Physical size (bytes) Logical size (bytes)
16
128
128
Memory configuration example
Rev. 07 — 29 September 2009
16
64
64
…continued
Endpoint description
16 bytes interrupt IN
double-buffered 64 bytes bulk OUT
double-buffered 64 bytes bulk IN
Table
Single-chip USB OTG controller
15), whether endpoints are
© ST-ERICSSON 2009. All rights reserved.
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