ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 108

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 112. DcAddress register: bit allocation
Table 114. DcMode register: bit allocation
[1]
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
15.1.3 DcMode register (R/W: B9h/B8h)
DEVEN
R/W
R/W
1
7
0
7
[1]
reserved
Table 113. DcAddress register: bit description
This command is used to access the DcMode register, which consists of 1 byte (bit
allocation: see
The DcMode register controls the DMA bus width, resume and suspend modes, interrupt
activity, and SoftConnect operation. It can be used to enable debug mode, in which all
errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write or read DcMode register
Transaction — write or read 1 byte (code or data)
Table 115. DcMode register: bit description
Bit
7
6 to 0
Bit
7 to 6
5
4
3
2
1
0
R/W
R/W
6
0
6
0
Symbol
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
Symbol
DEVEN
DEVADR[6:0]
Table
GOSUSP
R/W
R/W
Description
reserved
Writing logic 1 followed by logic 0 will activate suspend mode.
reserved
Logic 1 enables all interrupts. Bus reset value: unchanged.
Logic 1 enables debug mode, in which all NAKs and errors will generate an
interrupt. Logic 0 selects normal operation, in which interrupts are generated
on every ACK (bulk or interrupt endpoints) or after every data transfer
(isochronous endpoints). Bus reset value: unchanged.
reserved
Logic 1 enables SoftConnect. This bit is ignored if EXTPUL = 1 in the
DcHardwareConfiguration register (see
unchanged.
Remark: In OTG mode, this bit is ignored. The LOC_CONN bit of the
OtgControl register controls the pull-up resistor on the OTG_DP1 pin.
5
0
5
0
Rev. 07 — 29 September 2009
114). In 16-bit bus mode, the upper byte is ignored.
Description
Logic 1 enables the device.
This field specifies the USB device address.
reserved
R/W
R/W
4
0
4
0
DEVADR[6:0]
INTENA
R/W
R/W
0
3
0
3
[1]
DBGMOD
Single-chip USB OTG controller
Table
R/W
R/W
0
2
0
2
[1]
116). Bus reset value:
reserved
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
0
1
0
1
[1]
ISP1362
SOFTCT
108 of 147
R/W
R/W
0
0
0
0
[1]