ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 145

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.4
12.4.1
12.4.2
12.4.3
12.4.3.1
12.4.3.2
12.5
12.5.1
12.5.2
13
13.1
13.2
13.3
13.4
13.5
13.6
14
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.4
14.4.1
14.4.2
14.4.3
14.4.4
ISP1362_7
Product data sheet
OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Host controller registers . . . . . . . . . . . . . . . . . 67
Endpoint description . . . . . . . . . . . . . . . . . . . . 51
Endpoints with programmable buffer memory
size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Endpoint access . . . . . . . . . . . . . . . . . . . . . . . 51
Endpoint buffer memory size . . . . . . . . . . . . . 51
Endpoint initialization . . . . . . . . . . . . . . . . . . . 53
Endpoint I/O mode access . . . . . . . . . . . . . . . 53
Special actions on control endpoints . . . . . . . 53
Peripheral controller DMA transfer . . . . . . . . . 54
Selecting an endpoint for the DMA transfer . . 54
8237 compatible mode . . . . . . . . . . . . . . . . . . 54
End-Of-Transfer conditions. . . . . . . . . . . . . . . 56
Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 56
Isochronous endpoints . . . . . . . . . . . . . . . . . . 57
ISP1362 peripheral controller suspend and
resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Suspend conditions . . . . . . . . . . . . . . . . . . . . 57
Resume conditions . . . . . . . . . . . . . . . . . . . . . 59
OtgControl register (R/W: 62h/E2h) . . . . . . . . 59
OtgStatus register (R: 67h) . . . . . . . . . . . . . . . 61
OtgInterrupt register (R/W: 68h/E8h) . . . . . . . 62
OtgInterruptEnable register (R/W: 69h/E9h). . 64
OtgTimer register (R/W: 6Ah/EAh) . . . . . . . . . 65
OtgAltTimer register (R/W: 6Ch/ECh). . . . . . . 66
HC control and status registers . . . . . . . . . . . 69
HcRevision register (R: 00h). . . . . . . . . . . . . . 69
HcControl register (R/W: 01h/81h) . . . . . . . . . 69
HcCommandStatus register (R/W: 02h/82h) . 71
HcInterruptStatus register (R/W: 03h/83h) . . . 72
HcInterruptEnable register (R/W: 04h/84h) . . 73
HcInterruptDisable register (R/W: 05h/85h) . . 74
HC frame counter registers. . . . . . . . . . . . . . . 75
HcFmInterval register (R/W: 0Dh/8Dh). . . . . . 75
HcFmRemaining register (R/W: 0Eh/8Eh) . . . 76
HcFmNumber register (R/W: 0Fh/8Fh). . . . . . 77
HcLSThreshold register (R/W: 11h/91h). . . . . 78
HC root hub registers . . . . . . . . . . . . . . . . . . . 79
HcRhDescriptorA register (R/W: 12h/92h) . . . 79
HcRhDescriptorB register (R/W: 13h/93h) . . . 81
HcRhStatus register (R/W: 14h/94h) . . . . . . . 82
HcRhPortStatus[1:2] register (R/W [1]: 15h/95h;
[2]: 16h/96h) . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HC DMA and interrupt control registers . . . . . 87
HcHardwareConfiguration register (R/W:
20h/A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
HcDMAConfiguration register (R/W: 21h/A1h) 88
HcTransferCounter register (R/W: 22h/A2h). . 89
HcmPInterrupt register (R/W: 24h/A4h) . . . . . 90
Rev. 07 — 29 September 2009
14.4.5
14.5
14.5.1
14.5.2
14.5.3
14.6
14.6.1
14.6.2
14.6.3
14.7
14.7.1
14.7.2
14.7.3
14.7.4
14.8
14.8.1
14.8.2
14.8.3
14.8.4
14.8.5
14.8.6
14.8.7
14.9
14.9.1
14.9.2
14.9.3
14.9.4
14.9.5
14.9.6
14.9.7
14.9.8
14.9.9
15
15.1
15.1.1
15.1.2
15.1.3
15.1.4
15.1.5
15.1.6
15.1.7
15.1.8
15.2
Peripheral controller registers. . . . . . . . . . . 104
HcmPInterruptEnable register (R/W: 25h/A5h) 91
HC miscellaneous registers . . . . . . . . . . . . . . 92
HcChipID register (R: 27h). . . . . . . . . . . . . . . 92
HcScratch register (R/W: 28h/A8h) . . . . . . . . 93
HcSoftwareReset register (W: A9h) . . . . . . . . 93
HC buffer RAM control registers . . . . . . . . . . 93
HcBufferStatus register (R/W: 2Ch/ACh) . . . . 93
HcDirectAddressLength register
(R/W: 32h/B2h) . . . . . . . . . . . . . . . . . . . . . . . 94
HcDirectAddressData register (R/W: 45h/C5h) 95
Isochronous (ISO) transfer registers . . . . . . . 95
HcISTLBufferSize register (R/W: 30h/B0h) . . 95
HcISTL0BufferPort register (R/W: 40h/C0h) . 96
HcISTL1BufferPort register (R/W: 42h/C2h) . 96
HcISTLToggleRate register (R/W: 47h/C7h) . 97
Interrupt transfer registers . . . . . . . . . . . . . . . 97
HcINTLBufferSize register (R/W: 33h/B3h) . . 97
HcINTLBufferPort register (R/W: 43h/C3h) . . 97
HcINTLBlkSize register (R/W: 53h/D3h) . . . . 98
HcINTLPTDDoneMap register (R: 17h) . . . . . 98
HcINTLPTDSkipMap register (R/W: 18h/98h) 99
HcINTLLastPTD register (R/W: 19h/99h). . . . 99
HcINTLCurrentActivePTD register (R: 1Ah). 100
Control and bulk transfer (aperiodic transfer)
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
HcATLBufferSize register (R/W: 34h/B4h) . . 100
HcATLBufferPort register (R/W: 44h/C4h) . . 100
HcATLBlkSize register (R/W: 54h/D4h) . . . . 101
HcATLPTDDoneMap register (R: 1Bh) . . . . 101
HcATLPTDSkipMap register (R/W: 1Ch/9Ch) 102
HcATLLastPTD register (R/W: 1Dh/9Dh). . . 102
HcATLCurrentActivePTD register (R: 1Eh) . 102
HcATLPTDDoneThresholdCount register (R/W:
51h/D1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
HcATLPTDDoneThresholdTimeOut register
(R/W: 52h/D2h) . . . . . . . . . . . . . . . . . . . . . . 104
Initialization commands . . . . . . . . . . . . . . . . 106
DcEndpointConfiguration register (R/W:
30h to 3Fh/20h to 2Fh) . . . . . . . . . . . . . . . . 107
DcAddress register (R/W: B7h/B6h) . . . . . . 107
DcMode register (R/W: B9h/B8h). . . . . . . . . 108
DcHardwareConfiguration register (R/W:
BBh/BAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DcInterruptEnable register (R/W: C3h/C2h). . 110
DcDMAConfiguration (R/W: F1h/F0h) . . . . . . 111
DcDMACounter register (R/W: F3h/F2h) . . . . 112
Reset device (F6h). . . . . . . . . . . . . . . . . . . . . 113
Data flow commands . . . . . . . . . . . . . . . . . . . 113
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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