ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 49

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

12. USB peripheral controller
ISP1362_7
Product data sheet
12.1.1 IN data transfer
12.1.2 OUT data transfer
12.1 Peripheral controller data transfer operation
The design of the peripheral controller in the ISP1362 is compatible with the ST-Ericsson
ISP1181B USB full-speed interface device IC. The functionality of the peripheral controller
in the ISP1362 is similar to the ISP1181B in 16-bit bus mode. In addition, the command
and register sets are also the same.
In general, the peripheral controller in the ISP1362 provides 16 endpoints for the USB
device implementation. Each endpoint can be allocated RAM space in the on-chip ping
pong buffer RAM.
Remark: The ping pong buffer RAM for the peripheral controller is independent of the
buffer RAM for the host controller. When the buffer RAM is full, the peripheral controller
transfers the data in the buffer RAM to the USB bus. When the buffer RAM is empty, an
interrupt is generated to notify the microprocessor to feed in data. The transfer of data
between a microprocessor and the peripheral controller can be done in either
Programmed I/O (PIO) mode or in Direct Memory Access (DMA) mode.
The following sessions explain how the peripheral controller in the ISP1362 handles an IN
data transfer and an OUT data transfer. An IN data transfer means transfer from the
ISP1362 to an external USB host (through the upstream port), and an OUT transfer
means transfer from an external USB host to the ISP1362. In device mode, the ISP1362
acts as a USB device.
1. The arrival of the IN token is detected by the Serial Interface Engine (SIE) by
2. The SIE also checks the device number and the endpoint number to verify whether
3. If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus
4. After the data phase, the SIE expects a handshake (ACK) from the host (except for
5. On receiving the handshake (ACK), the SIE updates the contents of the
6. On receiving an interrupt, the microprocessor reads the DcInterrupt register. It knows
1. The arrival of the OUT token is detected by the SIE by decoding the PID.
2. The SIE checks the device and endpoint numbers to verify whether they are okay.
decoding the Packet Identifier (PID).
they are okay.
register (ESR). If the endpoint is full, the contents of the buffer memory are sent
during the data phase else an NAK handshake is sent.
ISO endpoints).
DcEndpointStatus and DcInterrupt registers, which in turn generates an interrupt to
the microprocessor. For ISO endpoints, the DcInterrupt register is updated as soon as
data is sent because there is no handshake phase.
which endpoint has generated the interrupt and reads the contents of the
corresponding ESR. If the buffer is empty, it fills up the buffer so that data can be sent
by the SIE at the next IN token phase.
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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