ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 55

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
Table 19.
The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller.
It operates as a ‘fly-by’ DMA controller. Data is not stored in the DMA controller, but it is
transferred between an I/O port and a memory address. A typical example of the
peripheral controller in 8237 compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA
(Hold Acknowledge). The bus operation is controlled by MEMR (Memory Read), MEMW
(Memory Write), IOR (I/O Read) and IOW (I/O Write).
The following example shows the steps that occur in a typical DMA transfer:
Symbol Description
DREQ2 DMA request of peripheral controller O
DACK2
EOT
RD
WR
1. The peripheral controller receives a data packet in one of its endpoint buffer memory.
2. The peripheral controller asserts the DREQ2 signal requesting the 8237 for a DMA
3. The 8237 requests the CPU to release the bus, by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places bus control signals
5. The 8237 now sets its address lines to 1234h, and activates the MEMW and IOR
6. The 8237 asserts DACK to inform the peripheral controller that it will start a DMA
Fig 26. Peripheral controller in 8327 compatible DMA mode
The packet must be transferred to memory address 1234h.
transfer.
(MEMR, MEMW, IOR and IOW) and address lines in 3-state, and asserts HLDA to
inform the 8237 that it has control of the bus.
control signals.
transfer.
DMA acknowledge of peripheral
controller
end of transfer
read strobe
write strobe
8237 compatible mode: pin functions
ISP1362
DREQ2
Rev. 07 — 29 September 2009
DACK2
D[15:0]
WR
RD
RAM
I/O Function
I
I
I
I
MEMR
MEMW
DREQ
DACK
IOR
IOW
CONTROLLER
peripheral controller requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs the peripheral controller to put data
on the bus
instructs the peripheral controller to get data
from the bus
DMA
8237
Single-chip USB OTG controller
HLDA
HRQ
Figure
© ST-ERICSSON 2009. All rights reserved.
HRQ
HLDA
26.
CPU
004aaa047
ISP1362
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