ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 141

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Special fields for ATL, interrupt and ISO . . . . .42
Table 11. Generic PTD structure: bit description . . . . . . .42
Table 12. CompletionCode[3:0]: bit description . . . . . . . .43
Table 13. ATL buffer area . . . . . . . . . . . . . . . . . . . . . . . .45
Table 14. Interrupt polling . . . . . . . . . . . . . . . . . . . . . . . .45
Table 15. Endpoint access and programmability . . . . . . .51
Table 16. Programmable buffer memory size . . . . . . . . .52
Table 17. Memory configuration example . . . . . . . . . . . .52
Table 18. Endpoint selection for the DMA transfer . . . . .54
Table 19. 8237 compatible mode: pin functions . . . . . . .55
Table 20. Summary of EOT conditions for a bulk
Table 21. Recommended EOT usage for isochronous
Table 22. OTG Control registers overview . . . . . . . . . . .59
Table 23. OtgControl register: bit allocation . . . . . . . . . .60
Table 24. OtgControl register: bit description . . . . . . . . .60
Table 25. OtgStatus register: bit allocation . . . . . . . . . . .61
Table 26. OtgStatus register: bit description . . . . . . . . . .61
Table 27. OtgInterrupt register: bit allocation . . . . . . . . .62
Table 28. OtgInterrupt register: bit description . . . . . . . .63
Table 29. OtgInterruptEnable register: bit allocation . . . .64
Table 30. OtgInterruptEnable register: bit description . . .64
Table 31. OtgTimer register: bit allocation . . . . . . . . . . . .65
Table 32. OtgTimer register: bit description . . . . . . . . . . .66
Table 33. OtgAltTimer register: bit allocation . . . . . . . . . .66
Table 34. OtgAltTimer register: bit description . . . . . . . .67
Table 35. Host controller registers overview . . . . . . . . . .67
Table 36. HcRevision register: bit allocation . . . . . . . . . .69
Table 37. HcRevision register: bit description . . . . . . . . .69
Table 38. HcControl register: bit allocation . . . . . . . . . . .69
Table 39. HcControl register: bit description . . . . . . . . . .70
Table 40. HcCommandStatus register: bit allocation . . . .71
Table 41. HcCommandStatus register: bit description . . .72
Table 42. HcInterruptStatus register: bit allocation . . . . .72
Table 43. HcInterruptStatus register: bit description . . . .73
Table 44. HcInterruptEnable register: bit allocation . . . . .73
Table 45. HcInterruptEnable register: bit description . . . .74
Table 46. HcInterruptDisable register: bit allocation . . . .75
ISP1362_7
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus access priority table for the ISP1362 . . . .13
Buffer memory areas and their applications . .14
I/O port addressing . . . . . . . . . . . . . . . . . . . . .20
Registers used in addressing modes . . . . . . . .25
Recommended capacitor values . . . . . . . . . . .38
Port 1 function . . . . . . . . . . . . . . . . . . . . . . . . .40
Generic PTD structure: bit allocation . . . . . . . .42
endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Rev. 07 — 29 September 2009
Table 47. HcInterruptDisable register: bit description . . . 75
Table 48. HcFmInterval register: bit allocation . . . . . . . . 76
Table 49. HcFmInterval register: bit description . . . . . . . 76
Table 50. HcFmRemaining register: bit allocation . . . . . 77
Table 51. HcFmRemaining register: bit description . . . . 77
Table 52. HcFmNumber register: bit allocation . . . . . . . . 78
Table 53. HcFmNumber register: bit description . . . . . . 78
Table 54. HcLSThreshold register: bit allocation . . . . . . 78
Table 55. HcLSThreshold register: bit description . . . . . 79
Table 56. HcRhDescriptorA register: bit allocation . . . . . 80
Table 57. HcRhDescriptorA register: bit description . . . . 80
Table 58. HcRhDescriptorB register: bit allocation . . . . . 81
Table 59. HcRhDescriptorB register: bit description . . . . 82
Table 60. HcRhStatus register: bit allocation . . . . . . . . . 82
Table 61. HcRhStatus register: bit description . . . . . . . . 83
Table 62. HcRhPortStatus[1:2] register: bit allocation . . 83
Table 63. HcRhPortStatus[1:2] register: bit description . 84
Table 64. HcHardwareConfiguration register: bit
Table 65. HcHardwareConfiguration register: bit
Table 66. HcDMAConfiguration register: bit allocation . . 88
Table 67. HcDMAConfiguration register: bit description . 89
Table 68. Buffer_Type_Select[2:0]: bit description . . . . . 89
Table 69. HcTransferCounter register: bit description . . 90
Table 70. HcmPInterrupt register: bit allocation . . . . . . . 90
Table 71. HcmPInterrupt register: bit description . . . . . . 90
Table 72. HcmPInterruptEnable register: bit allocation . . 92
Table 73. HcmPInterruptEnable register: bit description 92
Table 74. HcChipID register: bit description . . . . . . . . . . 93
Table 75. HcScratch register: bit description . . . . . . . . . 93
Table 76. HcSoftwareReset register: bit description . . . . 93
Table 77. HcBufferStatus register: bit allocation . . . . . . . 93
Table 78. HcBufferStatus register: bit description . . . . . . 94
Table 79. HcDirectAddressLength register: bit allocation 95
Table 80. HcDirectAddressLength register: bit
Table 81. HcDirectAddressData register: bit description 95
Table 82. HcISTLBufferSize register: bit description . . . 96
Table 83. HcISTL0BufferPort register: bit description . . . 96
Table 84. HcISTL1BufferPort register: bit description . . . 96
Table 85. HcISTLToggleRate register: bit allocation . . . . 97
Table 86. HcISTLToggleRate register: bit description . . . 97
Table 87. HcINTLBufferSize register: bit description . . . 97
Table 88. HcINTLBufferPort register: bit description . . . . 98
Table 89. HcINTLBlkSize register: bit allocation . . . . . . . 98
Table 90. HcINTLBlkSize register: bit description . . . . . . 98
Table 91. HcINTLPTDDoneMap register: bit description 99
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
continued >>
141 of 147