ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 88

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ISP1362BDTM

Manufacturer Part Number
ISP1362BDTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1362BDTM

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDTM
Manufacturer:
NANYA
Quantity:
1 001
Part Number:
ISP1362BDTM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Table 66.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
HcDMAConfiguration register: bit allocation
14.4.2 HcDMAConfiguration register (R/W: 21h/A1h)
15
-
-
Table 65.
Table 66
Code (Hex): 21 — read
Code (Hex): A1 — write
Bit
10
9
8
7
6
5
4 to 3
2
1
0
14
Symbol
AnalogOCEnable
OneINT
DACKMode
OneDMA
DACKInputPolarity
DREQOutputPolarity
DataBusWidth[1:0]
InterruptOutputPolarity
InterruptPinTrigger
InterruptPinEnable
-
-
contains the bit allocation of the HcDMAConfiguration register.
HcHardwareConfiguration register: bit description
13
-
-
Rev. 07 — 29 September 2009
12
-
-
Description
0 — use external overcurrent detection; digital input
1 — use on-chip overcurrent detection; analog input
0 — host controller interrupt routed to INT1, peripheral
controller interrupt routed to INT2
1 — host controller and peripheral controller interrupts routed
to INT1 only, INT2 is unused
0 — normal operation; DACK1 is used with read and write
signals
1 — reserved
0 — host controller DMA request and acknowledge are
routed to DREQ1 and DACK1, peripheral controller DMA
request and acknowledge are routed to DREQ2 and DACK2
1 — host controller and peripheral controller DMA requests
and acknowledges are routed to DREQ1 and DACK1;
DREQ2 and DACK2 unused
0 — DACK1 is active LOW
1 — DACK1 is active HIGH
0 — DREQ1 is active LOW
1 — DREQ1 is active HIGH
01 — microprocessor interface data bus width is 16 bits
Others — reserved
0 — INT1 interrupt is active LOW; power-up value
1 — INT1 interrupt is active HIGH
0 — INT1 interrupt is level-triggered; power-up value
1 — INT1 interrupt is edge-triggered
0 — power-up value
1 — global interrupt pin INT1 is enabled; this bit should be
used with the HcμPInterruptEnable register to enable
pin INT1
reserved
11
-
-
Single-chip USB OTG controller
10
-
-
…continued
© ST-ERICSSON 2009. All rights reserved.
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