ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 28

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
8.7.2 Interrupt in the peripheral controller
Interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the
HcInterruptStatus register). When any of these events occurs, the corresponding bit will
be set to logic 1, and if the corresponding bit in the HcInterruptEnable register is also
logic 1, the 6-input OR gate will output logic 1. This output is combined with the value of
MIE (bit 31 of HcInterruptEnable) using the AND operation and logic 1 output at this AND
gate will cause the OPR bit in the HcμPInterrupt register to be set to logic 1.
Interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in the
OtgInterrupt register). When any of these events occurs, the corresponding bit will be set
to logic 1, and if the corresponding bit in the OtgInterruptEnable register is also logic 1, the
11-input OR gate will output logic 1 and cause the OTG_IRQ bit in the HcμPInterrupt
register to be set to logic 1.
Level 1 interrupts contains 10 possible interrupt events. The HcμPInterrupt and
HcμPInterruptEnable registers work in the same way as the HcInterruptStatus and
HcInterruptEnable registers. The output from the 10-input OR gate is connected to a latch,
which is controlled by InterruptPinEnable (the bit 0 of HcHardwareConfiguration register).
When the software wishes to temporarily disable the interrupt output of the ISP1362 host
controller and OTG controller, follow this procedure:
To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1.
Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register controls the
latch of the interrupt output. When this bit is set to logic 0, the interrupt output will remain
unchanged, regardless of any operation on interrupt control registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal without
clearing the HcμPInterrupt register, follow this procedure:
To re-enable the interrupt generation:
The registers that control the interrupt generation in the ISP1362 peripheral controller are:
The DcMode register (bit 3) is the overall peripheral controller interrupt enable.
1. Set the InterruptPinEnable bit in the HcHardwareConfiguration register to logic 1.
2. Clear all bits in the HcμPInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
1. Make sure that the InterruptPinEnable bit is set to logic 1.
2. Clear all bits in the HcμPInterruptEnable register.
3. Set the InterruptPinEnable bit to logic 0.
1. Set all bits in the HcμPInterruptEnable register, according to the HCD requirements.
2. Set the InterruptPinEnable bit to logic 1.
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DcMode (bit 3)
DcHardwareConfiguration (bits 0 and 1)
DcInterruptEnable
DcInterrupt
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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