ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 29

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
8.7.4.1 Level-triggered interrupt
8.7.4.2 Edge-triggered interrupt
8.7.3 Combining INT1 and INT2
8.7.4 Behavior difference between level-triggered and edge-triggered interrupts
DcHardwareConfiguration determines the following features:
For details on the interrupt logic in the peripheral controller, refer to
Control application
In some embedded systems, interrupt inputs to the CPU are a very scarce resource. The
system designer might want to use just one interrupt line to serve the host controller, the
peripheral controller and the OTG controller. In such a case, make sure the OneINT
feature is activated.
When OneINT (bit 9 of the HcHardwareConfiguration register) is set to logic 1, both the
INT1 (HC or OTG controller) interrupt and the INT2 (peripheral controller) interrupt are
routed to pin INT1, thereby reducing the hardware resource requirements.
Remark: Both the host controller (or OTG controller) and the peripheral controller
interrupts must be set to the same polarity (active HIGH or active LOW) and the same
trigger type (edge or level). Failure to conform to this will lead to unpredictable behavior of
the ISP1362.
In many microprocessor systems, the operating system disables an interrupt when it is in
an Interrupt Service Routine (ISR). If there is an interrupt event during this period, it will
lead to level-triggered interrupt and edge-triggered interrupt.
When the ISP1362 interrupt asserts, the operating system takes no action because it
disables the interrupt when it is in the ISR. The interrupt line of the ISP1362 remains
asserted. When the operating system exits the ISR and re-enables the interrupt
processing, it sees the asserted interrupt line and immediately enters the ISR.
When the ISP1362 outputs a pulse, the operating system takes no action because it
disables the interrupt when it is in the ISR. The interrupt line of the ISP1362 goes back to
the inactive state. When the operating system exits the ISR and re-enables the interrupt
processing, it sees no pending interrupt. As a result, the interrupt is missed.
If the system needs to know whether an interrupt (approximately 160 ns pulse width)
occurs during this period, it may read the HcμPInterrupt register (see
•
•
Level-triggered or edge-triggered (bit 1)
Output polarity (bit 0)
note”.
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
Ref. 5 “Interrupt
© ST-ERICSSON 2009. All rights reserved.
Table
ISP1362
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