ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 75

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ISP1362BDTM

Manufacturer Part Number
ISP1362BDTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1362BDTM

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDTM
Manufacturer:
NANYA
Quantity:
1 001
Part Number:
ISP1362BDTM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Table 46.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptDisable register: bit allocation
14.2.1 HcFmInterval register (R/W: 0Dh/8Dh)
reserved
14.2 HC frame counter registers
R/W
MIE
31
23
15
0
7
-
-
-
-
-
-
Table 47.
The HcFmInterval register (bit allocation:
the bit time interval in a frame between two consecutive SOFs. In addition, it contains a
15-bit value, indicating the full-speed maximum packet size that the host controller may
transmit or receive without causing a scheduling overrun. The HCD may carry out minor
Bit
31
30 to 7
6
5
4
3
2
1
0
RHSC
R/W
30
22
14
6
0
-
-
-
-
-
-
HcInterruptDisable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
29
21
13
5
0
-
-
-
-
-
-
Rev. 07 — 29 September 2009
Description
Logic 0 is ignored by the host controller. Logic 1 disables interrupt
generation. This field is set after a hardware or software reset.
reserved
0 — ignore
1 — disable interrupt generation because of root hub status change
0 — ignore
1 — disable interrupt generation because of frame number overflow
0 — ignore
1 — disable interrupt generation because of unrecoverable error
0 — ignore
1 — disable interrupt generation because of resume detect
0 — ignore
1 — disable interrupt generation because of start-of-frame
reserved
0 — ignore
1 — disable interrupt generation because of scheduling overrun
R/W
UE
28
20
12
4
0
-
-
-
-
-
-
reserved
reserved
Table
reserved
R/W
RD
27
19
11
3
0
-
-
-
-
-
-
48) contains a 14-bit value that indicates
Single-chip USB OTG controller
R/W
SF
26
18
10
2
0
-
-
-
-
-
-
reserved
© ST-ERICSSON 2009. All rights reserved.
25
17
9
1
-
-
-
-
-
-
-
-
ISP1362
R/W
SO
75 of 147
24
16
8
0
0
-
-
-
-
-
-

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