ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 109

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 116. DcHardwareConfiguration register: bit allocation
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15.1.4 DcHardwareConfiguration register (R/W: BBh/BAh)
DAKOLY
reserved
R/W
15
7
0
-
-
This command is used to access the DcHardwareConfiguration register, which consists of
2 bytes. The first (lower) byte contains the device configuration and control values, the
second (upper) byte holds clock control bits and the clock division factor. The bit allocation
is given in
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during the suspend state, as well as output clock frequency,
DMA operating mode and pin configurations (polarity, signaling mode).
Code (Hex): BA/BB — write or read DcHardwareConfiguration register
Transaction — write or read 2 bytes (code or data)
Table 117. DcHardwareConfiguration register: bit description
Bit
15
14
13
12
11 to 8
7
6
DRQPOL
EXTPUL
R/W
R/W
14
0
6
1
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CKDIV[3:0]
DAKOLY
DRQPOL
Table
DAKPOL
116. A bus reset will not change any of programmed bit values.
NOLAZY
R/W
R/W
13
1
5
0
Rev. 07 — 29 September 2009
Description
reserved
Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used on
pin OTG_DP1 (in device mode) and that SoftConnect is not used. Bus
reset value: unchanged.
Logic 1 disables output on pin CLKOUT of the LazyClock frequency
(115 kHz ± 50 %) during the suspend state. Logic 0 causes pin CLKOUT
to switch to LazyClock output after approximately 2 ms delay, following the
setting of bit GOSUSP of the DcMode register. Bus reset value:
unchanged.
Logic 1 indicates that internal clocks are always running, even during the
suspend state. Logic 0 switches off the internal oscillator and PLL, when
they are not needed. During the suspend state, this bit must be made
logic 0 to meet suspend current requirements. The clock is stopped after a
delay of approximately 2 ms, following the setting of bit GOSUSP of the
DcMode register. Bus reset value: unchanged.
This field specifies clock division factor N, which controls the clock
frequency on output CLKOUT pin. The output frequency in MHz is given
by
15), with a reset value of 12 MHz (N = 3). The hardware design
guarantees no glitches during frequency change. Bus reset value:
unchanged.
Logic 1 selects DACK-only DMA mode. Logic 0 selects 8237 compatible
DMA mode. Bus reset value: unchanged.
Selects the DREQ2 pin signal polarity (0 = active LOW; 1 = active HIGH).
Bus reset value: unchanged.
48
⁄
(
CLKRUN
N
reserved
+
R/W
12
0
4
0
1
-
)
. The clock frequency range is 3 MHz to 48 MHz (N = 0 to
WKUPCS
R/W
R/W
11
0
3
0
reserved
Single-chip USB OTG controller
R/W
R/W
10
0
2
1
CKDIV[3:0]
INTLVL
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
1
1
0
ISP1362
INTPOL
109 of 147
R/W
R/W
8
1
0
0