ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 63

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
Table 28.
Bit
15 to 11
10
9
8
7
6
5
4
3
OtgInterrupt register: bit description
Symbol
-
OTG_TMR_
TIMEOUT
B_SE0_SRP This bit is set whenever the device detects more than 2 ms of SE0.
A_SRP_DET This bit is used to detect the Session Request Event (SRP) from the
OTG_
RESUME
OTG_
SUSPND
RMT_
CONN_C
B_SESS_
VLD_C
A_SESS_
VLD_C
Rev. 07 — 29 September 2009
Description
reserved
This bit is set whenever the OTG timer attains time-out. Writing logic 1
clears this bit. Writing logic 0 has no effect.
0 — no event
1 — OTG timer time-out
Writing logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — bus has been in SE0 for more than 2 ms
remote device. The SRP event can be either V
pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register determines
which SRP is selected. Writing logic 1 clears this bit. Writing logic 0
has no effect.
0 — no event
1 — SRP is detected
This bit is used to detect a J to K state change when the device is in
the suspend state. Writing logic 1 clears this bit. Writing logic 0 has no
effect.
0 — no event
1 — a resume signal (J → K) is detected when the bus is in the
suspend state
This bit is set whenever the OTG port goes into the suspend state (bus
idle for > 3 ms). Write logic 1 to clear this bit. Writing logic 0 has no
effect.
0 — no event
1 — suspend (bus idle for > 3 ms)
This bit is set whenever the RMT_CONN bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — RMT_CONN bit has changed
This bit is set whenever the B_SESS_VLD bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — bit B_SESS_VLD has changed
This bit is set whenever the A_SESS_VLD bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — bit A_SESS_VLD has changed
Single-chip USB OTG controller
BUS
© ST-ERICSSON 2009. All rights reserved.
pulsing or data line
ISP1362
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