ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 81

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ISP1362BDTM

Manufacturer Part Number
ISP1362BDTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1362BDTM

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDTM
Manufacturer:
NANYA
Quantity:
1 001
Part Number:
ISP1362BDTM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Table 58.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhDescriptorB register: bit allocation
14.3.2 HcRhDescriptorB register (R/W: 13h/93h)
31
23
15
7
-
-
-
-
-
-
-
-
Table 57.
The HcRhDescriptorB register is the second of two registers describing the characteristics
of the root hub. These fields are written during initialization to correspond to the system
implementation.
Code (Hex): 13 — read
Code (Hex): 93 — write
Bit
8
7 to 2
1 to 0
30
22
14
6
-
-
-
-
-
-
-
-
Symbol
PSM
-
NDP[1:0] NumberofDownstreamPort: These bits specify the number of downstream
HcRhDescriptorA register: bit description
Table 58
reserved
reserved
29
21
13
Description
PowerSwitchingMode: This bit is used to specify how the power switching
of Root Hub ports is controlled. It is implementation specific. This field is valid
only if the NoPowerSwitching (NPS) field is cleared.
0 — All ports are powered at the same time.
1 — Each port is individually powered. This mode allows port power to be
controlled by either the global switch or per-port switching. If the
PortPowerControlMask (PPCM) bit is set, the port responds to only port
power commands (Set/ClearPortPower). If the port mask is cleared, then the
port is controlled only by the global power switch (Set/ClearGlobalPower).
reserved
ports supported by the root hub. The ISP1362 supports two ports and
therefore, the value is 2.
5
-
-
-
-
-
-
-
-
Rev. 07 — 29 September 2009
shows the bit allocation of the register.
28
20
12
4
-
-
-
-
-
-
-
-
reserved
reserved
27
19
11
3
-
-
-
-
-
-
-
-
…continued
Single-chip USB OTG controller
R/W
R/W
26
18
10
2
-
-
-
-
PPCM[2:0]
DR[2:0]
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
25
17
IS
IS
9
1
-
-
-
-
ISP1362
R/W
R/W
81 of 147
24
16
8
0
-
-
-
-

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