ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 65

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 31.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
OtgTimer register: bit allocation
START_
13.5 OtgTimer register (R/W: 6Ah/EAh)
TMR
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 30.
Code (Hex): 6A — read
Code (Hex): EA — write
Bit
6
5
4
3
2
1
0
R/W
R/W
R/W
30
22
14
0
0
6
0
-
-
Symbol
OTG_SUSPND_IE
RMT_CONN_IE
B_SESS_VLD_IE
A_SESS_VLD_IE
B_SESS_END_IE
A_VBUS_VLD_IE
ID_REG_IE
OtgInterruptEnable register: bit description
R/W
R/W
R/W
29
21
13
0
0
5
0
-
-
Rev. 07 — 29 September 2009
TMR_INIT_VALUE[23:16]
TMR_INIT_VALUE[15:8]
Description
Logic 1 enables interrupt on detecting the bus suspend status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the RMT_CONN status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the B_SESS_VLD status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the A_SESS_VLD status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the B_SESS_END status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the A_VBUS_VLD status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the ID_REG status change.
Logic 0 disables interrupt.
TMR_INIT_VALUE[7:0]
R/W
R/W
R/W
28
20
12
0
0
4
0
-
-
reserved
R/W
R/W
R/W
27
19
11
0
0
3
0
-
-
…continued
Single-chip USB OTG controller
R/W
R/W
R/W
26
18
10
0
0
2
0
-
-
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R/W
25
17
0
9
0
1
0
-
-
ISP1362
R/W
R/W
R/W
65 of 147
24
16
0
8
0
0
0
-
-