ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 26

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
8.6.2 Combining the two DMA channels
8.7.1 Interrupt in the host controller and the OTG controller
8.7 Interrupts
Remark: Configure the HcDMAConfiguration register only after you have configured all
the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in this
register is set.
The ISP1362 allows systems with limited DMA channels to use a single DMA channel
(DMA1) for both the host controller and the peripheral controller. This option can be
enabled by writing logic 1 to the OneDMA bit of the HcHardwareConfiguration register. If
this option is enabled, the polarity of the peripheral controller DMA and the host controller
DMA must be set to DACK active LOW and DREQ active HIGH.
Various events in the host controller, the peripheral controller and the OTG controller can
be programmed to generate a hardware interrupt. By default, the interrupt generated by
the host controller and the OTG controller is routed out at the INT1 pin and the interrupt
generated by the peripheral controller is routed out at the INT2 pin.
There are two levels of interrupts represented by level 1 and level 2 (see
•
•
HcTransferCounter
– If DMACounterEnable of the HcDMAConfiguration register is set (that is, the DMA
HcDMAConfiguration
– Read or write DMA (bit 0)
– Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits 1 to 3)
– DMA enable or disable (bit 4)
– Burst length (bits 5 to 6)
– DMA counter enable (bit 7)
counter is enabled), HcTransferCounter must be set to the number of bytes to be
transferred.
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
Figure
14).
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