ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 107

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 110. DcEndpointConfiguration register: bit allocation
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
15.1.1 DcEndpointConfiguration register (R/W: 30h to 3Fh/20h to 2Fh)
15.1.2 DcAddress register (R/W: B7h/B6h)
FIFOEN
R/W
7
0
This command is used to access the DcEndpointConfiguration register (ECR) of the target
endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN),
buffer memory size and buffering scheme. It also enables the endpoint buffer memory.
The register bit allocation is shown in
The allocation of the buffer memory takes place only after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although control endpoints
have fixed configurations, they must be included in the initialization sequence and must
be configured with their default values (see
starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration that affects the allocated
memory (size, enable/disable), the buffer memory contents of all endpoints become
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoints 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 111. DcEndpointConfiguration register: bit description
This command is used to set the USB assigned address in the DcAddress register and
enable the USB device. The DcAddress register bit allocation is shown in
A USB bus reset sets the device address to 00h (internally) and enables the device. The
value of the DcAddress register (accessible by the microprocessor) is not altered by the
USB bus reset. In response to standard USB request Set Address, the firmware must
issue a Write Device Address command, followed by sending an empty packet to the host.
The new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write or read DcAddress register
Transaction — write or read 1 byte (code or data)
Bit
7
6
5
4
3 to 0
EPDIR
R/W
6
0
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
DBLBUF
R/W
5
0
Rev. 07 — 29 September 2009
Description
Logic 1 enables the FIFO buffer. Logic 0 disables the FIFO buffer.
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also determines
the DMA transfer direction (0 = read, 1 = write).
Logic 1 enables the double buffering.
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or
interrupt endpoint.
Selects the buffer memory size according to
FFOISO
R/W
4
0
Table
Table
R/W
110. A bus reset will disable all endpoints.
3
0
15). Automatic buffer memory allocation
Single-chip USB OTG controller
R/W
2
0
FFOSZ[3:0]
Table
16.
© ST-ERICSSON 2009. All rights reserved.
R/W
1
0
ISP1362
Table
112.
107 of 147
R/W
0
0