ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 30

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

9. Power-On Reset (POR)
ISP1362_7
Product data sheet
When V
will typically be 800 ns. The pulse is started when V
To give a better view of the functionality,
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short (that is, < 11 μs), the internal
POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at t0.
At t1, the detector will see the passing of the trip level and a delay element will add
another t
The internal POR pulse will be generated whenever V
11 μs.
The RESET pin can be either connected to V
externally controlled (by the micro, ASIC, and so on).
the clock with respect to the external reset pulse.
Fig 15. Internal power-on reset timing
Fig 16. Clock with respect to the external power-on reset
t0
CC
PORP
(1) PORP = Power-On Reset Pulse.
Stable external clock is available at A.
is directly connected to the RESET pin, the internal POR pulse width (t
t1
before it drops to LOW.
t
PORP
Rev. 07 — 29 September 2009
EXTERNAL CLOCK
RESET
t2
Figure 15
CC
t3
(using the internal POR circuit) or
t
PORP
A
shows a possible curve of V
CC
Figure 16
CC
rises above V
Single-chip USB OTG controller
drops below V
004aaa484
t4
shows the availability of
t5
© ST-ERICSSON 2009. All rights reserved.
trip
trip
(2.03 V).
ISP1362
for more than
004aaa482
PORP
V
V
CC
CC
trip
PORP
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(1)
with
)