ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 76

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 48.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmInterval register: bit allocation
14.2.2 HcFmRemaining register (R/W: 0Eh/8Eh)
R/W
R/W
R/W
FIT
31
23
15
0
0
7
1
-
-
reserved
adjustments on FrameInterval by writing a new value over the present one at each SOF.
This provides the programmability necessary for the host controller to synchronize with an
external clocking resource and to adjust any unknown local clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Table 49.
The HcFmRemaining register is a 14-bit down counter, showing the bit time remaining in
the current frame. The bit allocation is given in
Code (Hex): 0E — read
Bit
31
30 to 16
15 to 14
13 to 0
R/W
R/W
R/W
30
22
14
0
0
6
1
-
-
HcFmInterval register: bit description
Symbol
FIT
FSMPS
[14:0]
-
FI[13:0]
R/W
R/W
R/W
R/W
29
21
13
0
0
1
5
0
Rev. 07 — 29 September 2009
Description
FrameIntervalToggle: The HCD toggles this bit whenever it loads a
new value to FrameInterval.
FSLargestDataPacket: Specifies a value that is loaded into the
largest data packet counter at the beginning of each frame. The
counter value represents the largest amount of data in bits that can be
sent or received by the host controller in a single transaction at any
given time, without causing a scheduling overrun. The field value is
calculated by the HCD.
reserved
FrameInterval: Specifies the interval between two consecutive SOFs
in bit times. The nominal value is set to 11999. The HCD must store
the current value of this field before resetting the host controller.
Setting the HostControllerReset (HCR) field of the HcCommandStatus
register causes the host controller to reset this field to its nominal
value. The HCD may choose to restore the stored value on completing
the reset sequence.
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
1
FSMPS[7:0]
FI[7:0]
FSMPS[14:8]
R/W
R/W
R/W
R/W
27
19
11
0
0
1
3
1
Table
FI[13:8]
50.
Single-chip USB OTG controller
R/W
R/W
R/W
R/W
26
18
10
0
0
1
2
1
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
1
1
1
ISP1362
R/W
R/W
R/W
R/W
76 of 147
24
16
0
0
8
0
0
1