ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 142

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 92. HcINTLPTDSkipMap register: bit description .99
Table 93. HcINTLLastPTD register: bit description . . . . .99
Table 94. HcINTLCurrentActivePTD register: bit
Table 95. HcINTLCurrentActivePTD register: bit
Table 96. HcATLBufferSize register: bit description . . .100
Table 97. HcATLBufferPort register: bit description . . . .101
Table 98. HcATLBlkSize register: bit allocation . . . . . . .101
Table 99. HcATLBlkSize register: bit description . . . . . .101
Table 100.HcATLPTDDoneMap register: bit description 102
Table 101.HcATLPTDSkipMap register: bit description .102
Table 102.HcATLLastPTD register: bit description . . . . .102
Table 103.HcATLCurrentActivePTD register: bit
Table 104.HcATLCurrentActivePTD register: bit
Table 105.HcATLPTDDoneThresholdCount register: bit
Table 106.HcATLPTDDoneThresholdCount register: bit
Table 107.HcATLPTDDoneThresholdTimeOut register: bit
Table 108.HcATLPTDDoneThresholdTimeOut register: bit
Table 109.Peripheral controller command and register
Table 110. DcEndpointConfiguration register: bit
Table 111. DcEndpointConfiguration register: bit
Table 112. DcAddress register: bit allocation . . . . . . . . .108
Table 113. DcAddress register: bit description . . . . . . . .108
Table 114. DcMode register: bit allocation . . . . . . . . . . .108
Table 115. DcMode register: bit description . . . . . . . . . .108
Table 116. DcHardwareConfiguration register: bit
Table 117. DcHardwareConfiguration register: bit
Table 118. DcInterruptEnable register: bit allocation . . . . 110
Table 119. DcInterruptEnable register: bit description . . . 111
Table 120.DcDMAConfiguration register: bit allocation . 111
Table 121.DcDMAConfiguration register: bit description 112
Table 122.DcDMACounter register: bit allocation . . . . . . 112
Table 123.DcDMACounter register: bit description . . . . 112
Table 124.Endpoint buffer memory organization . . . . . . 113
Table 125.Example of endpoint buffer memory access . 114
Table 126.DcEndpointStatus register: bit allocation . . . . 114
Table 127.DcEndpointStatus register: bit description . . . 115
Table 128.DcEndpointStatusImage register: bit
Table 129.DcEndpointStatusImage register: bit
Table 130.DcErrorCode register: bit allocation . . . . . . . . 117
Table 131.DcErrorCode register: bit description . . . . . . . 117
Table 132.Transaction error codes . . . . . . . . . . . . . . . . . 117
Table 133.DcLock register: bit allocation . . . . . . . . . . . . 118
Table 134.DcLock register: bit description . . . . . . . . . . . 118
ISP1362_7
Product data sheet
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
description . . . . . . . . . . . . . . . . . . . . . . . . . . .100
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
description . . . . . . . . . . . . . . . . . . . . . . . . . . .103
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
description . . . . . . . . . . . . . . . . . . . . . . . . . . .103
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
description . . . . . . . . . . . . . . . . . . . . . . . . . . .104
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
description . . . . . . . . . . . . . . . . . . . . . . . . . . .107
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Rev. 07 — 29 September 2009
Table 135.DcScratch Information register: bit allocation 119
Table 136.DcScratch Information register: bit
Table 137.DcFrameNumber register: bit allocation . . . . 119
Table 138.DcFrameNumber register: bit description . . . 119
Table 139.Example of the DcFrameNumber register
Table 140.DcChipID register: bit allocation . . . . . . . . . . 120
Table 141.DcChipID register: bit description . . . . . . . . . 120
Table 142.DcInterrupt register: bit allocation . . . . . . . . . 121
Table 143.DcInterrupt register: bit description . . . . . . . . 121
Table 144.Limiting values . . . . . . . . . . . . . . . . . . . . . . . 122
Table 145.Recommended operating conditions . . . . . . 122
Table 146.Static characteristics: supply pins . . . . . . . . . 123
Table 147.Static characteristics: digital pins . . . . . . . . . 123
Table 148.Static characteristics: analog I/O pins
Table 149.Static characteristics: charge pump . . . . . . . 124
Table 150.Dynamic characteristics . . . . . . . . . . . . . . . . 127
Table 151.Dynamic characteristics: analog I/O
Table 152.Dynamic characteristics: charge pump . . . . . 127
Table 153.Dynamic characteristics: host controller
Table 154.Dynamic characteristics: peripheral controller
Table 155.Dynamic characteristics: host controller
Table 156.Dynamic characteristics: host controller burst
Table 157.Dynamic characteristics: peripheral controller
Table 158.Dynamic characteristics: peripheral controller
Table 159.Dynamic characteristics: peripheral controller
Table 160.Dynamic characteristics: peripheral controller
Table 161.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 162.Revision history . . . . . . . . . . . . . . . . . . . . . . . 140
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
lines (DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . 127
programmed interface timing . . . . . . . . . . . . 128
programmed interface timing . . . . . . . . . . . . 129
single-cycle DMA timing . . . . . . . . . . . . . . . . 131
mode DMA timing . . . . . . . . . . . . . . . . . . . . . 132
single-cycle DMA timing (8237 mode) . . . . . 133
single-cycle DMA read timing in DACK-only
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
single-cycle DMA write timing in DACK-only
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
burst mode DMA timing . . . . . . . . . . . . . . . . 135
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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