ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 45

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
11.5.1.4 Step 4
11.5.1.5 Step 5
11.6 Features of the interrupt transfer
11.7 Features of the Isochronous (ISO) transfer
The 16 bytes of data is now a complete PTD with an accompanying payload. This array is
then copied into the ATL buffer area.
Table 13.
After copying data into the ATL buffer, the host controller must be notified that the ATL
buffer is now full and ready to be processed. The ATL_Active bit of the HcBufferStatus
register must be set to logic 1 to inform the host controller that the data in the ATL buffer is
now ready for processing. Once the ATL_Active bit of the HcBufferStatus register is set,
the USB packet is sent out. The active bit in the PTD is cleared once the PTD is sent.
Depending on the outcome of the USB transfer, the 4-bit completion code is updated.
Table 14.
Offset
Data
N bits [7:5]
0
1
2
3
4
5
6
7
•
•
•
•
•
•
•
An interrupt transaction is periodically sent out, according to the ‘interrupt polling rate’
as defined in the PTD.
An interrupt transaction causes an interrupt to the CPU only if the transaction is
ACK-ed or has error conditions, such as STALL or no respond. An ACK condition
occurs if data is received on the IN token or data is sent out on the OUT token.
An interrupt is activated only once every ms as long as there is ACK for different
interrupt transactions in the interrupt transfer buffer.
Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or send
data for more than 1 ms. This can be done using the parameters in the PTD.
Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.
The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU
the flexibility to decide how much time it takes to read and fill in the ISO data.
The ISTL buffer can be updated on-the-fly by using the direct addressing memory
architecture.
ATL buffer area
Interrupt polling
StartingFrame N[4:0]
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
0
F800h
Rev. 07 — 29 September 2009
1
0008h
2
0008h
Table 13
3
0000h
shows the ATL buffer area.
Interrupt polling interval (2
1
2
4
8
16
32
64
128
4
0680h
Single-chip USB OTG controller
5
0100h
© ST-ERICSSON 2009. All rights reserved.
0000h
6
ISP1362
N
) in ms
7
0012h
45 of 147