ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 50

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
12.2.1 DMA for an IN endpoint (internal peripheral controller to the external USB
12.2.2 DMA for an OUT endpoint (external USB host to internal peripheral
12.2 Device DMA transfer
host)
When the internal DMA handler is enabled and at least one buffer (ping or pong) is free,
the DREQ2 line is asserted. The external DMA controller then starts negotiating for control
of the bus. As soon as it has access, it asserts the DACK2 line and starts writing data. The
burst length is programmable. When the number of bytes equal to the burst length has
been written, the DREQ2 line is deasserted. As a result, the DMA controller deasserts the
DACK2 line and releases the bus. At that moment, the whole cycle restarts for the next
burst.
When the buffer is full, the DREQ2 line is deasserted and the buffer is validated (which
means that it is sent to the host at the next IN token). When the DMA transfer is
terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated
when any of the following conditions is met:
Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
peripheral controller DMA controller handshake signals DREQ2 and DACK2 are routed to
DREQ1 and DACK1.
controller)
When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line
is asserted. The external DMA controller then starts negotiating for control of the bus. As
soon as it has access, it asserts the DACK2 line and starts reading data. The burst length
is programmable. When the number of bytes equal to the burst length has been read, the
DREQ2 line is deasserted. As a result, the DMA controller deasserts the DACK2 line and
releases the bus. At that moment, the whole cycle restarts for the next burst. When all the
data is read, the DREQ2 line is deasserted and the buffer is cleared (this means that it can
be overwritten when a new packet arrives). A DMA transfer is terminated when any of the
following conditions are met:
3. If the endpoint is enabled, the SIE checks the contents of the ESR. If the endpoint is
4. After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO
5. The SIE updates the contents of the DcEndpointStatus register and the DcInterrupt
6. On receiving an interrupt, the microprocessor reads the DcInterrupt register. It knows
•
•
empty, the data from USB is stored in the buffer memory during the data phase else a
NAK handshake is sent.
endpoints).
register, which in turn generates an interrupt to the microprocessor. For ISO
endpoints, the DcInterrupt register is updated as soon as data is received because
there is no handshake phase.
which endpoint has generated the interrupt and reads the content of the
corresponding ESR. If the buffer is full, it empties the buffer so that data can be
received by the SIE at the next OUT token phase.
The DMA count is complete.
DMAEN = 0.
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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