ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 87

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 64.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcHardwareConfiguration register: bit allocation
14.4.1 HcHardwareConfiguration register (R/W: 20h/A0h)
Suspend_
OneDMA
Wakeup
14.4 HC DMA and interrupt control registers
Disable
R/W
R/W
15
0
7
0
The bit allocation of the HcHardwareConfiguration register is given in
Code (Hex): 20 — read
Code (Hex): A0 — write
Table 65.
Bit
15
14
13
12
11
DACKInput
Polarity
Global
Power
Down
R/W
R/W
14
0
6
0
Symbol
DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the
GlobalPowerDown
ConnectPullDown_DS2
ConnectPullDown_DS1
SuspendClkNotStop
HcHardwareConfiguration register: bit description
PullDown
Connect
Polarity
Output
DREQ
_DS2
R/W
R/W
13
0
5
1
Rev. 07 — 29 September 2009
PullDown
Connect
_DS1
DataBusWidth[1:0]
R/W
R/W
12
0
4
0
Description
D_SUSPEND/D_WAKEUP and H_SUSPEND/H_WAKEUP
pins. Therefore, these pins will always remain HIGH and
pulling them LOW does not wake-up the host controller and
the peripheral controller.
Set this bit to logic 1 to reduce power consumption of the
OTG ATX in suspend mode.
0 — disconnect built-in pull-down resistors on H_DM2 and
H_DP2
1 — connect built-in pull-down resistors on H_DM2 and
H_DP2 for the downstream port 2
Remark: Port 2 is always used as a host port.
0 — disconnect built-in pull-down resistors on OTG_DM1 and
OTG_DP1
1 — connect built-in pull-down resistors on OTG_DM1 and
OTG_DP1
Remark: This bit is effective only when port 1 is configured as
the host port (the OTGMODE pin is HIGH, and the ID pin is
LOW). When port 1 is configured as the OTG port, (the
OTGMODE pin is LOW), the pull-down resistors on
OTG_DM1 and OTG_DP1 are controlled by the
LOC_PULL_DN_DP and LOC_PULL_DN_DM bits of the
OtgControl register.
0 — clock can be stopped when suspended
1 — clock cannot be stopped when suspended
ClkNotStop
Suspend
R/W
R/W
11
0
3
1
AnalogOC
Interrupt
Polarity
Enable
Single-chip USB OTG controller
Output
R/W
R/W
10
0
2
0
PinTrigger
Interrupt
OneINT
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
Table
9
0
1
0
ISP1362
64.
InterruptPin
Enable
DACK
Mode
R/W
R/W
87 of 147
8
0
0
0