ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 25

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
8.6.1 Configuring registers for a DMA transfer
8.6 Setting up a DMA transfer
Remark: The HcTransferCounter register counts the number of bytes even though the
transfer is in number of words. Therefore, the transfer counter must be set to word_size ×
2. Incorrect setting of the HcTransferCounter register may cause the ISP1362 to go into
an indeterminate state.
The buffer memory access using indirect addressing always starts from location 0 of each
buffer area. Only the front portion of the memory (example: first 64 bytes of a 1024 bytes
buffer) can be accessed. Therefore, to access a portion of the memory that does not start
from memory location 0, all memory locations before that location must be accessed in a
sequential order. The method is similar to the sequential file access method.
The ISP1362 uses two DMA channels to individually serve the host controller and the
peripheral controller. The DMA transfer allows the system CPU to work on other tasks
while the DMA controller transfers data to or from the ISP1362. The DMA slave controller,
in the ISP1362, is compatible with the 8327 type DMA controller.
The DMA transfer can be used with direct addressing mode or indirect addressing mode.
The registers used in these two modes are shown in
Table 6.
[1]
To set up a DMA transfer, the following host controller registers must be configured,
depending on the type of transfer required:
Addressing mode
Direct addressing
Indirect addressing
cnt=0;
do
{
outport(hc_data,*(a_ptr+cnt)); // hc_data is system address of HC
cnt++;
}
while(cnt<(word_size));
•
•
•
In direct addressing mode, HcTransferCounter must be set to 0001h.
HcHardwareConfiguration
– DREQ1 output polarity (bit 5)
– DACK1 input polarity (bit 6)
– DACK mode (bit 8)
HcμPInterruptEnable
– If you want an interrupt to be generated after the DMA transfer is complete, set
HcμPInterrupt
– Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set when
EOTInterruptEnable (bit 3).
the DMA transfer is complete.
Registers used in addressing modes
[1]
Rev. 07 — 29 September 2009
HcDMAConfiguration bit[3:1]
1XXB
0XXB
// data port
Table
Single-chip USB OTG controller
Total bytes to transfer
HcDirectAddressLength
HcTransferCounter
6.
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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