ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 115

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh)
15.2.4 Validate endpoint buffer (61h to 6Fh)
Table 127. DcEndpointStatus register: bit description
These commands are used to stall or unstall an endpoint. The commands modify the
content of the DcEndpointStatus register (see
A stalled control endpoint is automatically unstalled when it receives a set-up token,
regardless of the packet content. If the endpoint must stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by using the Unstall Endpoint command or by
receiving a set-up token), it is also re-initialized. This flushes the buffer: if it is an OUT
buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoints 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoints 1 to 14)
Transaction — none (code only)
This command signals the presence of valid data for transmission to the USB host. The
validation occurs by setting the Buffer Full flag of the selected IN endpoint. This indicates
that the data in the buffer is valid and can be sent to the host, when the next IN token is
received. For a double-buffered endpoint, this command switches the current buffer
memory for CPU access.
Remark: For special aspects of the control IN endpoint, see
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoints 1 to 14)
Transaction — none (code only)
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
Rev. 07 — 29 September 2009
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not
stalled).
Set to logic 1 by a stall endpoint command, cleared to logic 0 by an Unstall
Endpoint command. The endpoint is automatically unstalled on receiving
a set-up token.
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates data PID of the next packet (0 = DATA PID; 1 = DATA1
PID).
This bit is set by the hardware. Logic 1 indicates that a new set-up packet
has overwritten the previous set-up information, before it was
acknowledged or before the endpoint was stalled. Once writing of the
set-up data is completed, a read back of this register clears this bit.
The firmware must check this bit before sending an acknowledge set-up
command or stalling the endpoint. On reading logic 1, the firmware must
stop ongoing set-up actions and wait for a new set-up packet.
Logic 1 indicates that the buffer contains a set-up packet.
This bit indicates which buffer is currently selected for the CPU access
(0 = primary buffer; 1 = secondary buffer).
reserved
Table
126).
Single-chip USB OTG controller
Section
© ST-ERICSSON 2009. All rights reserved.
12.3.6.
ISP1362
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