ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 101

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 97.
Table 98.
ISP1362_7
Product data sheet
Bit
15 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcATLBufferPort register: bit description
HcATLBlkSize register: bit allocation
Symbol
DataWord[15:0] R/W
14.9.3 HcATLBlkSize register (R/W: 54h/D4h)
14.9.4 HcATLPTDDoneMap register (R: 1Bh)
R/W
15
7
0
-
-
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(44h to read from the ATL buffer, and C4h to write to the ATL buffer) to the host controller
through the I/O port of the microprocessor. After the command is sent, the HCD starts
reading data from the ATL buffer or writing data to the ATL buffer. While the HCD is
accessing the buffer, the buffer pointer of ATL also automatically increases. When the
pointer has reached the initialized byte count of the HcTransferCounter register, the host
controller sets the AllEOTInterrupt bit of the HcμPInterrupt register to logic 1 and updates
the HcBufferStatus register.
The ISP1362 partitions the ATL buffer into several equal sized blocks so that the host
controller can skip the current PTD and proceed to process the next PTD easily. The block
size of the ATL buffer must be specified in this register and must be a multiple of 8 bytes.
The bit allocation of the HcATLBlkSize register is given in
Code (Hex): 54 — read
Code (Hex): D4 — write
Table 99.
This is a 32-bit register. The bit description of the register is given in
of the register represents the processing status of a PTD. Bit 0 of the register represents
the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer,
and so on. The register is immediately updated after the completion of each ATL PTD
processing. It is cleared when read by the HCD. Bits that are set represent its
corresponding PTDs have been processed by the host controller and an ACK token has
been received from the device.
Code (Hex): 1B — read only
Bit
15 to 10
9 to 0
Access
R/W
14
6
0
-
-
HcATLBlkSize register: bit description
Symbol
-
BlockSize[9:0] The block size of the ATL buffer.
Value
0000h
R/W
13
5
0
-
-
Rev. 07 — 29 September 2009
reserved
Description
reserved
Description
Data of the ATL buffer to be accessed through this data port.
R/W
12
4
0
-
-
BlockSize[7:0]
R/W
11
3
0
-
-
Single-chip USB OTG controller
R/W
10
2
0
-
-
Table
98.
© ST-ERICSSON 2009. All rights reserved.
Table
R/W
R/W
9
0
1
0
BlockSize[9:8]
ISP1362
100. Every bit
101 of 147
R/W
R/W
8
0
0
0