US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 88

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 2 CPU
2.9
2.9.1
1. Access to Empty Areas:
2. Access to Internal I/O Registers:
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of
states in which on-chip peripheral modules can be accessed.
Rev. 8.00 Mar. 09, 2010 Page 66 of 658
REJ09B0042-0800
The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Data transfer from CPU to empty area:
Data transfer from empty area to CPU:
Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Word access from I/O register to CPU:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Unpredictable data is transferred.
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Application Notes
Notes on Data Access