US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 114

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 3 Exception Handling
3.3.5
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
Rev. 8.00 Mar. 09, 2010 Page 92 of 658
REJ09B0042-0800
interrupt request signal is sent to the interrupt controller.
the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2
for a list of interrupt priorities.)
is accepted; if the I bit is 1, the interrupt request is held pending.
External or
internal
interrupts
External
interrupts or
internal
interrupt
enable
signals
Interrupt Operations
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt controller
I
CCR (CPU)
Interrupt
request