US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 193

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
5. The time during which the P bit is set to 1 is the programming time. Figure 6.12 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
reprogramming data computation according to table 6.10, and additional programming data
computation according to table 6.11.
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
Do not use RTS instruction from data transfer to setting P bit to 1. (This does not apply to the
HD64F38124 and HD64F38122.)
allowable programming times.
An overflow cycle of approximately 6.6 ms is allowed.
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
Do not use RTS instruction from dummy write to verify data read. (This does not apply to the
HD64F38124 and HD64F38122.)
is 1,000.
Rev. 8.00 Mar. 09, 2010 Page 171 of 658
REJ09B0042-0800
Section 6 ROM