US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 578

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US38024-BAG1

Manufacturer Part Number
US38024-BAG1
Description
DEV EVALUATION KIT H8/38024
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet

Specifications of US38024-BAG1

Contents
2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
For Use With/related Products
H8/38024
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Appendix B Internal I/O Registers
LVDSR—Low-Voltage Detection Status Register
Note: This register is implemented on the H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 556 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Note: * These bits initialized by resets trigged by LVDR.
OVF
R/W
0 *
LVD Reference Voltage Stabilized Flag
7
0 [Clearing condition]
1 [Setting condition]
When 0 is written after reading 1
When the low-voltage detection counter (LVDCNT) overflows
Reference Voltage External Input Select
0 The on-chip circuit is used to generate the reference
1 The reference voltage is input to the Vref pin from
R/W
6
0
voltage
an external source
LVD Power Supply Voltage Drop Flag
0 [Clearing condition]
1 [Setting condition]
R/W
5
0
When 0 is written after reading 1
When the power supply voltage drops below Vint(D)
LVD Power Supply Voltage Rise Flag
R/W
0 [Clearing condition]
1 [Setting condition]
4
0
When 0 is written after reading 1
When the power supply voltage drops below
Vint(D) while the LVDUE bit in LVDCR is set
to 1, and it rises above Vint(U) before
dropping below Vreset1
VREFSEL
R/W
3
0
H'87
R/W
2
0
(initial value)
(initial value)
LVDDF
R/W
0 *
1
(initial v alue)
(initial value)
LVDUF
R/W
0 *
0
LVDC

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