US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 115

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

• If the interrupt request is accepted, after processing of the current instruction is completed,
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in
figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be
executed upon return from interrupt handling.
handling routine located at the address indicated by the contents of the vector address is
executed.
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
Rev. 8.00 Mar. 09, 2010 Page 93 of 658
Section 3 Exception Handling
REJ09B0042-0800