US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 590

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Appendix B Internal I/O Registers
SSR—Serial Status Register
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible.
Rev. 8.00 Mar. 09, 2010 Page 568 of 658
REJ09B0042-0800
Transmit Data Register Empty
0
1
Receive Data Register Full
0
1
Overrun Error
Transmit data written in TDR has not been transferred to TSR
[Clearing conditions] · After reading TDRE = 1, cleared by writing 0 to TDRE
Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions]
0
1
There is no receive data in RDR
[Clearing conditions] · After reading RDRF = 1, cleared by writing 0 to RDRF
There is receive data in RDR
[Setting condition] When reception ends normally and receive data is transferred from RSR to RDR
Framing Error
0
1
Reception in progress or completed
[Clearing condition] After reading OER = 1, cleared by writing 0 to OER
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF set to 1
Parity Error
0
1
Reception in progress or completed normally
[Clearing condition] After reading FER = 1, cleared by writing 0 to FER
A framing error has occurred during reception
[Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
Transmit End
0
1
Reception in progress or completed normally
[Clearing condition] After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception
[Setting condition]
R/(W) *
TDRE
Transmission in progress
[Clearing conditions]
Transmission ended
[Setting conditions]
7
1
· When data is written to TDR by an instruction
· When bit TE in serial control register3 (SCR3) is cleared to 0
· When data is transferred from TDR to TSR
· When RDR data is read by an instruction
reception, and the stop bit is 0
R/(W) *
RDRF
When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)
6
0
· After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
· When bit TE in serial control register3 (SCR3) is cleared to 0
· When bit TDRE is set to 1 when the last bit of a transmit character is sent
R/(W) *
OER
5
0
R/(W) *
FER
4
0
R/(W) *
PER
3
0
H'AC
TEND
R
2
1
⎯
R
1
0
R/W
⎯
0
0
SCI3